1700 V精细沟槽栅IGBT器件设计

为了改善绝缘栅双极型晶体管(IGBT)器件关断损耗和导通压降之间的折中关系,同时降低器件制造成本,基于1 700 V电压平台设计了一种采用精细沟槽栅结构的IGBT。采用TCAD软件进行仿真,研究衬底电阻率、衬底厚度、沟槽栅深度、沟槽栅宽度、载流子存储层注入剂量、沟槽栅元胞结构等因素对精细沟槽栅IGBT器件性能参数的影响,确定了最优工艺参数,并对1 700 V精细沟槽栅IGBT芯片进行流片和封装。测试结果显示,相比普通沟槽栅IGBT模块,1 700 V精细沟槽栅IGBT模块在芯片面积减小34.2%的情况下,关断损耗降低了8.6%,导通压降仅升高5.5%,器件性价比得到了优化。     

具有沟槽阳极短路的新型沟槽栅场截止绝缘栅双极晶体管

文章提出了一种新型的具有沟槽阳极短路的槽栅场截止型绝缘栅双极晶体管结构。通过引入沟槽短路阳极结构,器件的击穿电压得到了明显提高。仿真结果显示,相比于传统的场截止型绝缘栅双极晶体管,新结构提高了19.5 %的击穿电压,而且新结构具有更小的漏电流。在电流密度为150 A/cm2 时,新结构虽然提高了近百分之九的导通压降,但是关断时间只有传统结构的一半。此外,新结构导通时没有负阻效应。因此,新结构具有更好的关断功耗与导通压降的折中关系。     

IGBT全自对准栅挖槽工艺研究

设计了一种全自对准槽栅IGBT(绝缘栅双极晶体管)结构，其工艺简单，全套工艺只有两张光刻版，提高了工艺成品率。它独特的IGBT沟道多重短路结构，有效地防止了器件闩锁；采用氧化层硬掩膜和硅化物工艺，实现了全自对准的多晶硅反刻和金属连接，增加了IGBT芯片单位面积的元胞密度和沟道宽度，提高了器件的电流能力；用砷(As)掺杂代替磷(P)掺杂，有效地提高了源区表面浓度，实现了浅结工艺。     

3300V逆导型IGBT器件仿真

基于现有仿真平台,设计一款3 300V/50A逆导型绝缘栅双极晶体管器件(逆导型IGBT或RC-IGBT),元胞采用场截止型平面栅结构,元胞设计中采用载流子增强技术(EP),元胞注入采用自对准工艺,背面P型集电极采用透明集电极技术,降低IGBT工作模式下的饱和压降。采用二维数值仿真研究了器件结构及结构参数对器件性能的影响,通过结构参数拉偏,折衷优化IGBT与内集成二极管的性能参数,仿真得到的3 300V/50A逆导型IGBT器件饱和压降为3.4V,二极管导通压降为2.3V,阈值电压为5.6V,击穿电压为4 480V,与相同电压等级的分立IGBT器件和二极管性能相当。     

高压Trench IGBT的研制

介绍了当前绝缘栅双极晶体管(IGBT)的几种结构及沟槽型IGBT的发展现况,分析了高电压沟槽型非穿通(NPT)IGBT的结构及工艺特点。通过理论分析计算出初步器件的相关参数,再利用ISE仿真软件模拟器件的结构及击穿和导通特性,结合现有沟槽型DMOS工艺流程,确定了器件采用多分压环加多晶场板的复合终端、条状元胞、6μm深度左右沟槽、低浓度背面掺杂分布与小于180μm厚度的器件结构,可以很好地平衡击穿特性与导通特性对器件结构的要求。成功研制出1 200 V沟槽型NPT系列产品,并通过可靠性考核,经过电磁炉应用电路实验,结果表明IGBT器件可稳定工作,满足应用要求。该设计可适合国内半导体生产线商业化生产。     

沟槽栅IGBT非晶Si填槽工艺研究与优化

采用低压化学气相淀积(LPCVD)非晶Si填槽工艺代替LPCVD多晶Si填槽工艺,对沟槽绝缘栅双极型晶体管(IGBT)器件的沟槽进行非晶Si回填,研究并优化了高深宽比非晶Si填槽工艺.分析了LPCVD非晶Si工艺参数如PH3体积流量和沉积时间等对LPCVD非晶Si填槽能力的影响,通过调制P掺杂浓度和优化非晶Si淀积时间,得到槽底侧壁与槽口侧壁非晶Si厚度差值为0.022 μm的基准非晶Si填槽工艺,优化了LPCVD非晶Si反复多次填槽工艺条件.结果表明,采用优化后的工艺可实现沟槽栅IGBT器件沟槽非晶Si无缝回填,器件的栅极电阻降低了0.150 Ω,漏电流降低了1.408 nA,成品率提升了0.4％.     

1 200 V沟槽栅场截止型IGBT终端设计

利用二维半导体工艺及器件模拟工具,从结掺杂浓度、P阱与P环间距、P环尺寸控制3个方面分析了半绝缘多晶硅终端结构的击穿电压,提出了应用于1 200 V沟槽栅场截止型IGBT的终端解决方案。从结的深度和终端长度两方面,将SIPOS终端技术与标准的场环场板终端技术进行了对比。结果表明,采用SIPOS终端结构并结合降低表面场技术,使得终端尺寸有效减小了58%,并且,采用SIPOS技术的终端区域击穿电压受结深的影响较小,有利于实际制造工艺的控制和IGBT器件稳定性的提升。     

3300 V FS型IGBT器件研制

基于现有仿真及工艺平台,设计一款3 300V/50A场截止型绝缘栅双极晶体管器件(FS-IGBT),元胞采用场截止型平面栅结构,元胞注入采用自对准工艺,背面P型集电极采用透明集电极技术,降低导通状态的饱和压降。采用二维数值仿真主要研究了FS结构以及P~+集电极掺杂参数对器件性能的影响,通过参数拉偏仿真,重点分析了FS层和集电极P区注入剂量对器件参数的影响,确认了最佳的工艺窗口条件。通过合作方工艺平台对最终的结构进行了加工,最终测试结果显示IGBT器件通态压降为2.8V,击穿电压大于4 250V,关断损耗37mJ,开通损耗50mJ。     

具有P型浮空区的槽栅IGBT结构

本文提出了一种具有P型浮空层的新型槽栅IGBT结构,它是在之前所提的一种积累层沟道控制的槽栅IGBT(TAC-IGBT)基础之上引入了一浮空P型层。此结构在维持原有TAC-IGBT低的正向导通压降和更大正向偏置安全工作区（FBSOA）的同时,减小了器件的泄漏电流,提高了器件的击穿电压,也使得器件的短路安全工作区大大提高,且制造简单,设计裕度增大。仿真结果表明：对于1200V的IGBT器件,具有P型浮空层的新型槽栅IGBT结构漏电比TAC-IGBT小近一个量级,击穿电压提高近150V。     

全自对准槽栅IGBT设计

本文设计了一种全自对准的楷栅IGBT(绝缘栅双极晶体管)结构，其工艺简单，全套工艺只有两块光刻版，且两次光刻之间没有套刻关系，避免了套刻误差，提高了工艺成品率。同时，降低了制版费用和制造成本。我们设计了一种独特的IGBT多重沟道短路结构，有效地防止器件闩锁。用氧化层硬掩模和先进的硅化物工艺实现全自对准的多晶硅反刻和金属连接，可使元胞尺寸缩小到2μm甚至更小；增加了IGBT芯片单位面积的元胞密度和沟道宽度，提高了电流。用砷(As)掺杂代替磷(P)，可有效提高源区表面浓度，实现浅结工艺。     

Stacked Gate FinFET with Gate Extension for Improved Gate Control

Russian Microelectronics - Referring to the experimental data available, a modified pile gate bulk FinFET device with trapezoidal cross-section is analyzed through this paper. Two special features...     

Al栅a—Si TFT栅绝缘膜研究

Ａｌ栅可明显降低ＡＭ－ＬＣＤ中ａ－Ｓｉ ＴＦＴ矩阵的栅总线电阻及栅脉冲信号延迟，有利于提高高密显示屏的开口率与图像质量。本文详细分析了Ａｌ栅的阳极氧化技术，获得了适于ａ－Ｓｉ ＴＦＴ复合栅的Ａｌ２Ｏ３栅绝缘材料。     

Gate CD Control Considering Variation of Gate and STI Structure

We developed a fab-wide advanced process control system to control the critical dimension (CD) of gate electrode length in semiconductors. We also developed a model equation that predicts the gate CD by considering the structures of gate electrode and shallow trench isolation. This prediction model was also used to perform a factor analysis of gate CD variation. The effectiveness of the model in controlling feedforward was evaluated by both simulation and experiment. The CD variation of the wafers was improved from 8.9 nm in its 3 sigma without control to 3.5 nm with lot-to-lot feedforward control.     

浮栅器件栅耦合系数修正的探讨

提取浮栅器件栅耦合率的方法一般都是针对不可忽略的沟道耦合现象进行修正.对这些方法进行了比较、分析发现,对于短沟道浮栅器件,会由于参考器件存在明显的DIBL/SIBL效应,使提取的源、漏耦合系数偏大产生了很大的误差.提出了一种对亚阈值斜率法提取浮栅器件栅耦合系数的修正方法,结合了DIBL/SIBL效应因子,基于亚阈值斜率之比来较简单地实现更精确的近似,得到的栅耦合系数与设计值吻合较好,误差在2%以内,表明此修正法是合理且精确的.     

300门CMOS／SIMOX门阵列容错ASIC电路的研制

本文简要地介绍了３μｍＣＭＯＳ／ＳＩＭＯＸ门阵列的设计和制作技术。利用３００门门阵列母片成功地实现了容错计算机系统专用总线输出选择逻辑电路ＳＥＬ。其性能达到了用户要求，平均单级门延迟时间为２．６ｎｓ，输出驱动电流为２．４ｍＡ．     

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here.     

纳米双栅MOSFET栅极漏电流的二维量子模拟(英文)

基于非平衡格林函数(NEGF)的量子输运理论框架,对双栅MOSFET进行了二维实空间数值模拟。在对表征载流子电势的泊松方程自洽求解后,感兴趣的物理量(如亚阈值摆幅、漏致势垒下降、载流子密度、电流密度等)可以被求得,观察了由栅极注入效应导致的二维电荷分布,并对不同电介质材料对栅极漏电流的影响进行了研究。此外,还通过调整电介质参数并进行比较的方法,研究了电介质的有效质量、介电常数、导带偏移对栅极漏电流的影响。该模拟方法为双栅MOSFET中载流子自栅极的注入提供了良好的物理图景,对器件特性的分析和比较有助于栅氧层高k电介质材料的选取。     

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

Transparent Gate Silicon Photodetectors

Optical and electrical properties of silicon imaging devices with In/sub 2/O/sub 3/-SnO/sub 2/ gates are reported. The optically transparent electrically conducting films were sputtered from both glass and metal targets. Quantum efficiencies of such devices are significantly better than photodiodes or polysilicon gate devices. The electrical properties such as dark current and interface state density are as low as conventional aluminum gate devices after appropriate anneals.     

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO _x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high-κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO _x -Ge quantum dots.