深亚微米SOI工艺SoC设计中天线效应的消除

深亚微米SOI片上系统芯片(SoC)因其工艺特性,按照常规的布局布线(PNR)流程,出现了约一万个天线效应违规。介绍了一种在布局布线阶段不插入反偏二极管就可以消除大量天线效应违规的优化迭代流程。通过对天线效应的产生以及天线比率公式的分析,从线长和栅面积角度考虑天线效应的修复,结合自动布局布线设计工具SoC Encounter对这些因素的控制,可以在布局布线阶段消除天线效应的违规,并能与版图验证的结果保持一致。在一款通用抗辐照SoC芯片的设计中,应用该优化流程在布局布线阶段消除了设计中的天线效应违规,有效节约了芯片整体设计时间。     

蓝牙专用集成电路芯片及其后端实现

蓝牙是一种短距离无线连接技术，具有广阔的应用范围和巨大的市场。自动布局布线工具使得芯片设计者更有效的利用时间并大大加速了产品投向市场。介绍了蓝牙芯片的后端设计。     

基于ASIC实现蓝牙基带芯片的后端设计

从ASIC设计的原理、流程入手，以蓝牙基带芯片的后端设计为例，介绍用自动布局布线工具实现半定制专用集成电路(ASIC)设计。通过版图规划(F1oorplan)、布局(Place)、布线(Route)、静态分析和优化等过程，讨论了后端设计过程中可能遇到的问题及解决方法。     

自制IP模块的后端版图设计

介绍利用synopsys公司建库工具Milkyway，制作IP模块Milkyway库的方法和流程，以及采用ASIC设计领域流行的后端布局布线工具Astro，进行带有自制IP模块的版图自动布局布线的方法扣流程，并给出了设计实例。     

基于Astro的MIC总线控制器专用集成电路后端设计

本文介绍了采用当前ASIC设计领域内流行的后端布局布线工具-Astro，进行MIC总线控制器远程模块专用集成电路的设计过程。     

基于MS-ECO的多模式多端角签收时序修复方法的研究

为了使现代超大规模数字芯片物理设计在签收阶段更快、更好地达到时序收敛,基于MS-ECO时序修复引擎,结合后端签收工具Tempus的精确度和后端实现工具Innovus的高效性,采用分布式多模式多端角时序分析,提出了一种跨平台签收阶段自动时序修复方法。在3个不同工艺的数字芯片上验证了该方法。结果表明,该方法平均能使时序违例路径减少86%,并使WNS降低72%,TNS降低89%。同时,该时序修复方法没有引入新的设计规则违例(DRV)。     

百万门系统级芯片的后端设计

采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战,如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂,使百万门级芯片版图设计师需深入物理设计,选用有效EDA工具,结合电路特点开发有针对性的后端设计流程。文章介绍了采用Synopsys公司Astro后端工具对一款百万门级、基于0.18μm工艺SoC芯片后端设计的过程,分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍。同时考虑到深亚微米工艺下的互联线效应,介绍了如何预防串扰问题以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求。     

一款深亚微米ASIC芯片的后端设计

采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战,如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂,使芯片版图设计师需深入介入物理设计,选用有效的EDA工具,结合电路特点开发有针对性的后端设计流程。文章介绍了采用Cadence公司Soc Encounter后端工具对基于0.18μm工艺的ASIC芯片后端设计过程,分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍。同时考虑到深亚微米工艺下的互联线效应,介绍了如何预防串扰问题,以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求。     

卫星导航抗干扰专用芯片后端版图设计

随着电磁环境的日益复杂,卫星导航接收系统的抗干扰性能要求越来越高。在小型卫导接收系统的抗干扰设计中,体积和功耗已经成为最大的限制因素,抗干扰芯片的设计已成为解决该问题的有效途径。本文基于SoC Encounter后端版图设计工具,通过布局规划、电源设计、标准单元放置、时钟树综合及优化、布线等后端版图设计流程,完成了一款卫星导航抗干扰专用芯片的后端版图设计工作。     

Synopsys:强强联手更显优势

前段时间，Synopsys宣布购并Avant!一事引起业界的广泛关注。最近，借来京参加微电子论坛之际，Synopsys总裁兼COO陈志宽先生与专业媒体进行了座谈，介绍了公司的发展战略。陈先生表示，Synopsys一直在逻辑综合领域保持领先地位。但采用0.18mm或更小生产工艺以后，传统的逻辑综合与布局布线分开设计的方式会导致两者之间的循环反复，已不再适用。所以Synopsys决定发展物理综合技术，将前端的逻辑综合与后端的布局布线统一起来。Synopsys在综合工具领域占有近90%的市场份额，而Avant!的布局布线工具也拥有43%的市场份额。合并后，Synops…     

A general time model for the specification and design of embedded real-time systems

Design of complex embedded systems feasible with current and upcoming semiconductor technologies necessitates consideration of real-time from the beginning. However, the commonly used specification techniques do not consider temporal aspects in general like fulfillment of high level timing requirements or dynamic reactions on timing violations. In this paper, we discuss the restrictions of current specification techniques for embedded real-time systems and present a general time model that solves this issue. The time model contains the progress of time, the measurement of time and the specification of timing requirements based on event traces. In contrast to earlier techniques, preconditions determine the actual relevance of a specific timing bound. Exemplified for SDL, a solution for the specification of temporal aspects is shown. The advantages of this solution are discussed in a hardware/software co-design case study from the mobile communication area.     

时序冲突及时序检查

本文介绍一个多相同步时序数字电路的时序模型及时序冲突的检验算法。该方法能检查出时序冲突类型，冲突的具体位置及时钟系统设置的合理性。该算法已在Ｓｕｍ－４／ＳＰＡＲＣ上实现，能快速准确检查出非覆盖多相时钟同时时序电路存在的时序冲突，冲突覆盖率高。     

Scan Chain Hold-Time Violations: Can They be Tolerated?

Scan chain hold-time violations may occur due to manufacturing defects or to errors in timing closure process during the physical design stage. The latter type of violations prohibits the test of manufactured chips, leading to a zero yield, although these chips with scan hold-time violations may be perfectly functional. In this paper, we propose a suite of techniques which enable the diagnosis and the tolerance of scan hold-time violations. The proposed diagnosis technique can be utilized for any scan chain hold-time violation in order to pinpoint, in minimal diagnosis application time, the cause of the violation. The proposed tolerance technique is more targeted towards violations that lead to systematic failure of parts; it enables the generation of test patterns to screen out the defective parts in the presence of scan hold-time violations, perfectly restoring the yield in a cost-effective manner. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. We also extend this discussion for fast-to-rise and fast-to-fall errors, intermittent scan hold-time violations, and functional hold-time violations.      

High-speed demonstration of single-flux-quantum cross-bar switch up to 50 GHz

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.     

中国的毫秒脉冲星计时观与建议

回顾了国际上脉冲星计时观测研究的进展与成果,评述了中国的毫秒脉冲星计时的学术观和进展,给出了应用小波分析方法在研究时间尺度方面的创新性成果。深思了进行高精度计时需进一步研究的一些问题,并对国际间合作进行脉冲星计时与应用研究的工程问题等提出建议。     

一种基于锁存器实现时序收敛的方法

扫描链测试,作为一种简单、高效的可测性设计方法,已经广泛应用于集成电路设计中。该方法可以有效地检测出电路制造过程中的缺陷和故障,从而降低芯片的测试成本。但是随着扫描链的插入,芯片物理设计中的时序收敛变得更加复杂,尤其是在扫描链测试的移位模式下,由于时钟偏移的存在,保持时间可能存在大量的时序违例。针对这种情况,本文首先介绍了扫描链测试的基本原理,分析了插入扫描链之后出现保持时间违例的原因,提出了一种基于锁存器的修复时序违例的方法,并详细阐述了对于不同边沿触发的触发器组如何选择相应的锁存器实现时序收敛。最后,将该方法应用于一款电力通信芯片的物理设计,快速、高效地实现了时序的收敛。     

激光诱导等离子体多色谱应用

本文全面讨论了当前激光诱导等离子体多色谱的主要应用。从多色谱需求的提出出发，到当前的基本应用，对多色谱采集装置，处理方法、应用原理进行了全面的论述，对激光诱导等离子体多色谱的国内外应用现状进行了详尽的分析。主要包括估算电子温度、电子密度；进行化学分析、痕量探测等方面的应用。     

带间与带内串扰的理论分析与实验研究

在波分复用(WDM)系统中不同信道之间的串扰将恶化每路信号的消光比,而多波长光交叉连接网络中还会出现带内串扰的情况,它所产生的拍频噪声对系统的影响远大于带间串扰。从不同的角度分析了这两种串扰,理论分析的结果与实验现象吻合良好。     

When Online Meets Offline: An Expectancy Violations Theory Perspective on Modality Switching

The present study examines the occurrence and timing of modality switching (MS) from the perspective of expectancy violations theory. The results indicate that, relative to continuing to interact through computer-mediated communication, participants rated the social information (partner behavior and physical appearance/attractiveness) acquired by MS as an expectancy violation, although their evaluations varied as a function of the timing of the switch. Participants evaluated the social information more positively and uncertainty-reducing following short-term online associations but more negatively and uncertainty-provoking following long-term ones compared to remaining online. Moreover, social information acquired through MS, irrespective of the timing, was rated as more relationally important. Implications and limitations of the results as well as directions for future research are discussed.     

ECO技术在SoC芯片设计中的应用

在现阶段的SoC芯片设计中,有一半以上的芯片设计由于验证问题需要重新修改,这其中包括功能、时序以及串扰等问题。芯片设计的整个流程都要进行验证工作,工程改变命令（ECO,EngineeringChangeOrder）用于解决芯片设计后期发现的部分问题。本文重点分析了华大九天EDA工具TimingExplorer在解决时序以及串扰等问题上的部分ECO应用。