硼离子选择注入制备多孔硅微阵列

根据p型硅和n型硅不同的制备多孔硅的工艺条件,利用硼离子选择注入,在n型硅片上的局部微区域,形成易于腐蚀的p型硅,用电化学腐蚀方法制备出图形化的多孔硅阵列.省去了传统掩膜腐蚀工艺的掩膜材料的选取与制备以及后道工艺中掩膜材料的清除等工艺,克服了掩膜材料掩蔽效果较差以及存在横向钻蚀等缺点.通过AFM,SEM测试,证明该方法的效果很好.     

一维纳米硅光子晶体的制备与优化

采用双槽电化学腐蚀法制备了纳米多孔硅,主要研究了腐蚀时间和腐蚀电流对重掺杂p型(100)硅衬底上制备的多孔硅层有效光学厚度的影响,采用U-4100光谱仪、场发射扫描电子显微镜(FESEM)技术对所制备的多孔硅光子晶体的结构和有效光学厚度进行了分析表征。研究结果表明,通过合理地选择腐蚀时间和腐蚀电流,可以比较精确地制备特定有效光学厚度的多孔硅薄膜,此方法可广泛应用于纳米多孔硅光子晶体的制备中。     

用电化学腐蚀法制备氧化多孔硅波导定向耦合器

用一种聚合物材料薄膜作为掩膜 ,通过在电化学腐蚀过程中控制腐蚀电流和时间 ,首次制备出了氧化多孔硅波导定向耦合器。实验中用波长为 980nm的激光作为信号光源 ,观测到了样品的耦合光信号。给出了耦合器耦合系数不确定的因素 ,同时也分析了多孔硅波导传输损耗形成的原因。     

多孔硅场致电子发射

研究了多孔硅冷阴极的场致电子发射特性，实验表明采用电化学阳极腐蚀、氧化、蒸电极等工艺可以制备一种平面薄膜型多孔硅冷阴极。在超高真空环境下测量了多孔硅冷阴极的电子发射特性。     

基于微机械的多孔硅牺牲层技术

多孔硅作为一种牺牲层材料 ,在表面硅微机械加工技术中有着重要的应用。文中综合讨论了三种不同的多孔硅牺牲层技术 ,并用后两种“在低掺杂衬底上的多孔硅牺牲层技术”,制作了良好的悬空微薄膜结构 ,同时对多孔硅表面的薄膜淀积 ,和制备过程中的掩膜材料等进行了分析 ,为利用多孔硅工艺制作各种 MEMS器件奠定了基础。     

电化学脉冲腐蚀法制备窄峰发射的多孔硅微腔

用电化学脉冲腐蚀方法制备了多孔硅微腔,讨论了脉冲电化学腐蚀的参数--周期、占空比对多孔硅多层膜制备的影响,并用了以HF酸扩散为基础的多孔硅动态腐蚀机理对实验结果进行解释,认为在用电化学脉冲腐蚀法制备多孔硅微腔的过程中,不但要考虑到HF酸对硅的纵向电流腐蚀,也要考虑到HF酸对多孔硅硅柱的横向浸泡腐蚀.可通过选取合适的周期、占空比,使二者对多孔硅的作用达到适中,以制备出高质量的多孔硅多层膜和微腔.并用正交实验法优化了制备多孔硅微腔的参数,根据优化的实验参数,制备出了发光峰半峰宽为6nm的多孔硅微腔.     

电化学脉冲腐蚀法制备窄峰发射的多孔硅微腔

用电化学脉冲腐蚀方法制备了多孔硅微腔,讨论了脉冲电化学腐蚀的参数--周期、占空比对多孔硅多层膜制备的影响,并用了以HF酸扩散为基础的多孔硅动态腐蚀机理对实验结果进行解释,认为在用电化学脉冲腐蚀法制备多孔硅微腔的过程中,不但要考虑到HF酸对硅的纵向电流腐蚀,也要考虑到HF酸对多孔硅硅柱的横向浸泡腐蚀.可通过选取合适的周期、占空比,使二者对多孔硅的作用达到适中,以制备出高质量的多孔硅多层膜和微腔.并用正交实验法优化了制备多孔硅微腔的参数,根据优化的实验参数,制备出了发光峰半峰宽为6nm的多孔硅微腔.     

电化学脉冲腐蚀法制备窄峰发射的多孔硅微腔

用电化学脉冲腐蚀方法制备了多孔硅微腔 ,讨论了脉冲电化学腐蚀的参数——周期、占空比对多孔硅多层膜制备的影响 ,并用了以 HF酸扩散为基础的多孔硅动态腐蚀机理对实验结果进行解释 ,认为在用电化学脉冲腐蚀法制备多孔硅微腔的过程中 ,不但要考虑到 HF酸对硅的纵向电流腐蚀 ,也要考虑到 HF酸对多孔硅硅柱的横向浸泡腐蚀 .可通过选取合适的周期、占空比 ,使二者对多孔硅的作用达到适中 ,以制备出高质量的多孔硅多层膜和微腔 .并用正交实验法优化了制备多孔硅微腔的参数 ,根据优化的实验参数 ,制备出了发光峰半峰宽为 6 nm的多孔硅微腔     

多孔硅的化学浸蚀制备与表征

以不同电阻率的p型单晶硅片为研究对象,通过正交实验对化学浸蚀法制备多孔硅的工艺条件进行优化,采用多种仪器对制备的多孔硅比表面积、膜厚、表面形貌、化学组成及光致发光进行表征.结果表明,p型单晶硅片经化学浸蚀后能够形成多孔硅,其膜厚达到3 μm;延长浸蚀时间,多孔硅比表面积和膜厚呈先增大后减小的趋势,但化学浸蚀时间太长将导致局部区域的多孔硅层坍塌;室温条件下,多孔硅可光致发光,由于孔洞尺寸分布范围较窄,多孔硅发光半峰宽较窄.     

适用于高品质射频集成电感的多孔硅新型衬底制备技术

提出了背向选区腐蚀生长多孔硅的集成电感衬底结构.ASITIC模拟证明,该新型衬底结构的集成电感在高频下仍具有较高的品质因子.采用此工艺,在固定腐蚀液配比的条件下,变化电流密度和阳极氧化时间,制备出了高质量的厚膜多孔硅,并测量了多孔硅的生长厚度、孔径大小和表面形貌,得出了多孔硅生长速率随阳极氧化时间和电流密度的变化关系,为背向选区腐蚀工艺制备高品质硅基集成电感奠定了理论和实验基础.     

用于MEMS的选择性形成多孔硅技术的研究

提出了一套采用扩散工艺在低掺杂的硅衬底上选择性形成多孔硅牺牲层,并制作了MEMS器件结构的工艺流程,进行了工艺流水.对得到的结果进行了详细的讨论.对于KOH溶液释放多孔硅牺牲层技术进行了研究.     

用于制备SOI材料的基于硅片键合和双层多孔硅剥离的薄外延硅膜转移技术

采用在阳极化反应时改变电流强度的办法 ,在高掺杂的 P型硅 (111)衬底上制备了具有不同多孔度的双层结构多孔硅层 .用超高真空电子束蒸发技术在多孔硅表面外延生长了一层高质量的单晶硅膜 .在室温下 ,该外延硅片同另一生长有热二氧化硅的硅片键合在一起 ,在随后的热处理过程中 ,键合对可在多孔硅处裂开 ,从而使外延的单晶硅膜转移到具有二氧化硅的衬底上以形成 SOI结构 .扫描电镜、剖面投射电镜、扩展电阻和霍尔测试表明 SOI样品具有较好的结构和电学性能     

微结构制备中选择性多孔硅牺牲层技术的研究

利用多孔硅形成的选择性。在指定的硅衬底区域制作多孔硅作牺牲层，提出了制作微结构，后进行阳极氧化，形成多孔硅牺牲层的工艺，由此制备出了良好的悬空结构，并对多孔硅形成的选择性、掩模材料和工艺条件进行了研究。     

Shallow trench isolation based on selective formation of oxidized porous silicon

We have studied the porous silicon (PS) formation dependence on the substrate doping concentration as a selective tool to form locally oxidized regions in silicon wafers. This approach could be used for electrical isolation in CMOS circuits as a promising alternative to the shallow trench isolation STI process which begins to show some limitations (voiding and dishing) for the most advanced technologies.     

FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's

Processing steps of FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's are presented, FIPOS technology realizes a silicon-on-insulator structure, utilizing thick porous oxidized silicon and donors produced by proton implantation. New processing steps are proposed which provides small surface step and are suitable for LSI fabrication. Formation conditions of thick porous oxidized silicon are established by density control technique for porous silicon using a newly developed anodization system. CMOS devices are fabricated in isolated silicon layers and it is shown that the characteristics of n-channel and p-channel MOSFETS's are sufficient for application to CMOS LSI's. A FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology. These results indicate that FIPOS technology is very useful for realizing high-performance CMOS LSI's.     

Low-stress hybridisation of emitters,detectors and driver circuitry on a silicon motherboard for optoelectronic interconnect architecture

In the absence of a truly integrated silicon optoelectronics technology, manufacturable hybridisation technologies for III–V optoelectronic components, compatible with silicon and CMOS substrates, are essential for optoelectronic interconnect. The hybridisation technology for a clock distribution optical interconnect architecture is reported. A substrate removal technology for an 8×8 array of 10 μm thick VCSEL coupons is described, and the performance of AlAs and AlGaAs etch stop layers is discussed. Optoelectronic systems which depend on the retention of the polarisation specific nature of components restrict the mechanical constraints on their manipulation and bonding, to avoid stresses which could destroy the polarisation specificity of the component. A low-stress pick and place technology using a mask aligner has been employed. Eight hundred and fifty nanometres top-surface emitting GaAs/AlGaAs VCSELs, InGaAs/InP p–i–n photodiode arrays, and high-frequency CMOS silicon driver chips have been hybridised on silicon motherboards using this technology. The factors influencing the choice of bonding materials and the sequence of component hybridisation, including the requirements of subsequent planarisation and wiring processes, are discussed. The sources of alignment error are reported. Examples of working emitters, detectors and driver circuitry hybridised using this technology are presented.     

双槽电化学腐蚀法制备多孔硅的研究

论述了多孔硅的特点和制备方法,简单介绍双槽电化学腐蚀法的特点,并采用双槽电化学腐蚀法成功制备了多孔硅。多孔硅的扫描电镜(SEM)照片表明,孔径尺寸小,均匀性好,腐蚀结构规则。实验结果表明,衬底导电类型影响着多孔硅的制备条件。     

A new dielectric isolation method using porous silicon

A new dielectric isolation technology is proposed. In the new structure, single crystalline Si islands are separated from the silicon substrate by oxidized porous silicon. It is based on the following characteristics of the porous silicon oxide formation: (1) p-type Si is more easily changed to porous silicon than n-type Si; (2) porous silicon is formed along the anodic reaction current flow line; (3) the change in volume of porous silicon after oxidation is relatively small; (4) thick porous silicon films (10 μm) can be obtained easily. In this method, a p-type isolated layer is obtained by proton implantation used for an n-type layer formation. Lateral p-n junctions fabricated in such isolated silicon layers show lower leakage current than those reported in SOS technology.     

Large‐area epitaxial silicon solar cells based on industrial screen‐printing processes

Thin‐film epitaxial silicon solar cells are an attractive future alternative for bulk silicon solar cells incorporating many of the process advantages of the latter, but on a potentially cheap substrate. Several challenges have to be tackled before this potential can be successfully exploited on a large scale. This paper describes the points of interest and how IMEC aims to solve them. It presents a new step forward towards our final objective: the development of an industrial cell process based on screen‐printing for > 15% efficient epitaxial silicon solar cells on a low‐cost substrate. Included in the discussion are the substrates onto which the epitaxial deposition is done and how work is progressing in several research institutes and universities on the topic of a high‐throughput epitaxial reactor. The industrial screen‐printing process sequence developed at IMEC for these epitaxial silicon solar cells is presented, with emphasis on plasma texturing and improvement of the quality of the epitaxial layer. Efficiencies between 12 and 13% are presented for large‐area (98 cm²) epitaxial layers on highly doped UMG‐Si, off‐spec and reclaim material. Finally, the need for an internal reflection scheme is explained. A realistically achievable internal reflection at the epi/substrate interface of 70% will result in a calculated increase of 3 mA/cm² in short‐circuit current. An interfacial stack of porous silicon layers (Bragg reflectors) is chosen as a promising candidate and the challenges facing its incorporation between the epitaxial layer and the substrate are presented. Experimental work on this topic is reported and concentrates on the extraction of the internal reflection at the epi/substrate interface from reflectance measurements. Initial results show an internal reflectance between 30 and 60% with a four‐layer porous silicon stack. Resistance measurements for majority carrier flow through these porous silicon stacks are also included and show that no resistance increase is measurable for stacks up to four layers. Copyright © 2005 John Wiley & Sons, Ltd.