一种新型4H-SiC BJT结终端结构研究

设计了一种应用于4H-SiC BJT的新型结终端结构。该新型结终端结构通过对基区外围进行刻蚀形成单层刻蚀型外延终端,辅助耐压的p+环位于刻蚀型外延终端的表面,采用离子注入的方式,与基极接触的p+区同时形成。借助半导体数值分析软件SILVACO,对基区外围的刻蚀厚度和p+环的间距进行了优化。仿真分析结果表明,当刻蚀厚度为0.8μm,环间距分别为8,10和9μm时,能获得最高击穿电压。新结构与传统保护环(GR)和传统结终端外延(JTE)相比,BVCEO分别提高了34%和15%。利用该新型终端结构,得到共发射极电流增益β>47、共发射极击穿电压BVCEO为1 570V的4H-SiC BJT器件。     

新结构InGaP/GaAs/InGaP DHBT生长及特性研究

设计并生长了一种新的InGaP/GaAs/InGaP DHBT结构材料,采用在基区和集电区之间插入n+-InGaP插入层结构,以解决InGaP/GaAs/InGaP DHBT集电结导带尖峰的电子阻挡效应问题。采用气态源分子束外延(GSMBE)技术,通过优化生长条件,获得了高质量外延材料,成功地生长出带有n+-InGaP插入层结构的GaAs基InGaP/GaAs/InGaP DHBT结构材料。采用常规的湿法腐蚀工艺,研制出发射极面积为100μm×100μm的新型结构InGaP/GaAs/InGaP DHBT器件。直流特性测试的结果表明,所设计的集电结带有n+-InGaP插入层的InGaP/GaAs/InGaP DHBT器件开启电压约为0.15V,反向击穿电压达到16V,与传统的单异质结InGaP/GaAs HBT相比,反向击穿电压提高了一倍,能够满足低损耗、较高功率器件与电路制作的要求。     

提高微波功率双极晶体管性能的研究

通过对硅S波段微波功率双极晶体管的结终端技术实验数据对比和晶体管镇流电阻设计的考虑,提高了微波功率双极器件的击穿电压和电流通过能力及抗烧毁能力。微波器件采用这些技术后,器件的工作频率不但没有降低,反而从原来的S波段的低端(2.25～2.55 GHz),提高到了中高端(3.1～3.5 GHz);器件的集电结反向击穿电压50 V以上的比率由原来的17.6%提高到63.5%;器件的功率增益也从6 dB提高到7.5 dB以上,证明了该工艺方法的有效性与可行性。     

一种超结高压肖特基势垒二极管

改善反向击穿电压和正向导通电阻之间的矛盾关系一直以来都是功率半导体器件的研究热点之一。介绍了一种超结肖特基势垒二极管(SJ-SBD),将p柱和n柱交替构成的超结结构引入肖特基势垒二极管中作为耐压层,在保证正向导通电阻足够低的同时提高了器件的反向耐压。在工艺上通过4次n型外延和4次选择性p型掺杂实现了超结结构。基于相同的外延层厚度和相同的外延层杂质浓度分别设计和实现了常规SBD和SJ-SBD,测试得到常规SBD的最高反向击穿电压为110 V,SJ-SBD的最高反向击穿电压为229 V。实验结果表明,以超结结构作为SBD的耐压层能保证正向压降等参数不变的同时有效提高击穿电压,且当n柱和p柱中的电荷量相等时SJ-SBD的反向击穿电压最高。     

外延层厚度对垂直结构6H-SiC光导开关特性影响的研究

设计了新颖的具有垂直结构的6H-SiC光导开关。首先采用离子注入工艺在半绝缘6H-SiC衬底两侧生成一层p+离子注入层,然后利用外延工艺在其中的一侧生长一层n+外延层,并将此侧定义为开关的阴极。利用二维半导体器件仿真软件,研究了n+外延层厚度对6H-SiC光导开关特性的影响。结果表明,增加外延层厚度可以提高开关的击穿电压;而开关的导通电流,首先随着n+外延层厚度的增加而减小,在n+外延层厚度为5?m达到最小值,随后随着厚度的增加,导通电流增加。     

不同集电结结构的AlGaInP/GaAs异质结双极晶体管

设计并制备了三种不同集电结结构的A lG aInP/G aA s异质结双极晶体管,计算给出了三种集电结能带结构。通过对三种HBT的直流特性测试表明,N pN型HBT因异质集电结的导带尖峰出现电子阻挡效应;N p iN型HBT集电结引入i-G aA s层能有效克服电子阻挡效应,同时还具有拐点电压Vknee小、开启电压Voffset小、击穿电压BVCEO大等优点,但由于i-G aA s层引入增加了基区电子扩散长度,使器件电流增益有所下降。     

标准CMOS工艺低压栅控硅发光器件设计与制备

本文采用0.18μm标准CMOS工艺设计并制备了一种MOS结构的低压栅控硅基发光器件.该光源器件内部采用n+-p+-p+-n+-p+-p+-n+的叉指结构,在相邻两个p+有源区之间覆盖多晶硅栅作为第三端控制电极,用于在源/漏区边缘形成场诱导结,降低p+/n-well结的反向击穿电压,提高器件发光功率.测试结果表明,该光源器件可以发射420nm～780nm的黄色可见光,在3V的正向栅压下,p+/n-well发光二极管的反向击穿电压下降到3V以下,光输出功率提高至2倍以上.本文设计的光源器件工作电压较低,并且与CMOS工艺完全兼容,可以与其他CMOS电路共用电源并且实现单片集成,在硅基光电子集成领域具有一定的应用价值.     

基于双极载流子导电的新型恒流器件

提出了一种基于双极载流子导电、具有低开启电压VK和高反向击穿电压BVR的恒流器件,并进行了初步的试验验证。利用Tsuprem4和Medici仿真工具对器件的恒定电流IS、开启电压VK、正向击穿电压BVF和反向击穿电压BVR等电学参数进行了仿真,优化了外延层电阻率ρepi、外延层厚度Tepi、JFET注入剂量DJFET、P-well注入窗口间距WJFET等参数。试验结果显示,该器件工作于正向时,开启电压VK约为1.6 V,恒定电流IS约为31 mA,正向击穿电压BVF为55 V;该器件工作在反向时,反向击穿电压BVR约为200 V。     

4H-SiC npn BJT特性研究

基于二维器件仿真软件Medici对4H-SiC双极型晶体管(BJT)进行了建模，包括能带模型、能带窄变模型、迁移率模型、产生复合模型和不完全电离模型，为4H—SiC的工艺与器件提供了设计平台．在此基础上对4H—SiC BJT器件进行了模拟研究．结果显示，器件基极电流IB=1μA／μm时发射极电流增益β为32．4，击穿电压BVCEO大于800V，截止频率fr，接近1GHZ．     

高频4H-SiC双极晶体管的研制

研制出国内第一个高频4H-SiC双极晶体管.该器件采用了双台面结构和叉指结构,室温下的最大直流电流增益(β)为3.25,集电结击穿电压BVCBO达200 V.器件的β随温度的升高而降低,具有负的温度系数,这种特性使该器件容易并联,避免出现热失控现象.器件的高频特性由矢量网络分析仪测量得到,截止频率.fT为360 MHz、最高振荡频率fmax为160 MHz.     

An implanted-emitter 4H-SiC bipolar transistor with high currentgain

An epi-base, implanted-emitter, npn bipolar transistor which showed a maximum common emitter current gain (β) of ~40, the highest current gain reported for BJT in any polytype of SiC has been experimentally demonstrated in 4H-SiC. The forward drop was ~1 V at forward current density of 50 A/cm². The current gain decreases hence specific on-resistance increases with increasing temperature. The negative temperature coefficient of β makes the device attractive for paralleling and for preventing thermal runaways     

High current gain 4H-SiC npn bipolar junction transistors

The authors report a common emitter current gain /spl beta/ of 55 in npn epitaxial-emitter 4H-SiC bipolar junction transistors. The spacing between the p+ base contact implant and the edge of the emitter finger is critical in obtaining high-current gain. V/sub CEO/ of these devices is 500 V, and V/sub CBO/ is 700 V.     

High-voltage implanted-emitter 4H-SiC BJTs

Implanted-emitter, epi-base, npn 4H-SiC bipolar junction transistors (BJTs) which show maximum blocking voltage of 500 V and common-emitter current gain (β) of 8 are demonstrated. Compared to the previous results (BV_CEO of 60 V and β of 40), the blocking voltage is greatly improved with reduced current gain due to a decrease of the base transport factor. The samples also show negative temperature coefficient of β, similar to the previous samples, easing device paralleling problems     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

4H-SiC npn BJT特性研究

基于二维器件仿真软件Medici对4H-SiC双极型晶体管(BJT)进行了建模,包括能带模型、能带窄变模型、迁移率模型、产生复合模型和不完全电离模型,为4H-SiC的工艺与器件提供了设计平台.在此基础上对4H-SiC BJT器件进行了模拟研究.结果显示,器件基极电流I_B=1μA/μm时发射极电流增益β为32.4,击穿电压BV_CEO大于800V,截止频率f_T接近1GHZ.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

3300V碳化硅肖特基二极管及混合功率模块研制

基于数值仿真结果,采用结势垒肖特基(JBS)结构和多重场限环终端结构实现了3 300 V/50 A 4H-SiC肖特基二极管(SBD),所用4H-SiC外延材料厚度为35 μm、n型掺杂浓度为2× 1015cm-3.二极管芯片面积为49 mm2,正向电压2.2V下电流达到50 A,比导通电阻13.7 mΩ· cm2;反偏条件下器件的雪崩击穿电压为4 600 V.基于这种3 300 V/50 A 4H-SiC肖特基二极管,研制出3 300 V/600 A混合功率模块,该模块包含24只3 300 V/50 A Si IGBT与12只3 300 V/50 A 4H-SiC肖特基二极管,SiC肖特基二极管为模块的续流二极管.模块的动态测试结果为:反向恢复峰值电流为33.75 A,反向恢复电荷为0.807 μC,反向恢复时间为41 ns.与传统的Si基IGBT模块相比,该混合功率模块显著降低了器件开关过程中的能量损耗.     

Implantation-Free 4H-SiC Bipolar Junction Transistors With Double Base Epilayers

This letter reports the first 4H-SiC power bipolar junction transistor (BJT) with double base epilayers which is completely free of ion implantation and hence of implantation-induced crystal damages and high-temperature activation annealing-induced surface roughness. Based on this novel design and implantation-free process, a 4H-SiC BJT was fabricated to reach an open base collector-to-emitter blocking voltage of over 1300 V, with a common-emitter current gain up to 31. Improvements on reliability have also been observed, including less forward voltage drift (< 2%) and no significant degradation on current gain in the active region.