单电子晶体管的Ⅰ-Ⅴ特性数学模型及逻辑应用

基于正统单电子理论,提出了单电子晶体管的Ⅰ-Ⅴ特性数学算法改进模型.该模型的优点是考虑了背景电荷的影响,可由实际物理参数直接获得,支持双栅极工作,便于逻辑电路的分析.研究了背景电荷和各物理参数对Ⅰ-Ⅴ特性及跨导的影响,讨论了双栅极单电子晶体管的逻辑应用简化了"异或"逻辑电路,改进了二叉判别图电路的逻辑单元.     

基于主方程法单电子晶体管的Verilog-A行为模型

 基于单电子晶体管的主方程算法,在简化Lientschnig的单电子晶体管模型基础上,建立了基于Verilog-A的单电子晶体管行为描述模型,并利用Cadence Spectre 仿真器对该模型进行了验证.通过单电子晶体管逻辑电路的设计和仿真,表明该模型具有合理的精确度,且速度快,为单电子晶体管电路及混合电路的仿真提供了一种有效的方法.     

单电子晶体管的I-V特性数学模型及逻辑应用

基于正统单电子理论，提出了单电子晶体管的I-V特性数学算法改进模型。该模型的优点是：考虑了背景电荷的影响，可由实际物理参数直接获得，支持双栅极工作，便于逻辑电路的分析。研究了背景电荷和各物理参数对I-V特性及跨导的影响，讨论了双栅极单电子晶体管的逻辑应用：简化了“异或”逻辑电路，改进了二叉判别图电路的逻辑单元。     

单电子晶体管用于电荷检测的研究

单电子晶体管可用作超灵敏电荷计进行高灵敏电荷检测。首先建立了单电子晶体管电荷检测的电路模型,阐释了其电荷检测机制;然后利用COMSOL和MATLAB软件对检测过程进行了模拟研究,分析了不同电荷量和检测距离时单电子晶体管库仑岛的电势,并研究了电荷量、检测距离及电荷间静电耦合对单电子晶体管电导的影响。结果表明,单电子晶体管电荷检测时工作点和检测距离决定其电荷检测的量程,最佳检测距离应设置在电导-距离曲线的斜率最大处。     

纳米器件与单电子晶体管(续)

6单电子晶体管的集成单电子晶体管的集成化将依赖于各元器件的无线耦合[3],这与传统的大规模集成电路原理不同.基于这种单电子器件的集成原理,Nakazato等人[4,5]实现了有存储功能的单电子存储器和单电子逻辑电路.它们通过单电子晶体管间的隧穿耦合和电容耦合来实现单电子器件的集成.     

太赫兹探测器读出电路的单电子晶体管制备

射频单电子晶体管具有高电荷灵敏度和高读出速率的特点,可用于超导太赫兹单光子探测器产生的微弱电荷信号的读出。采用绝缘体上硅(SOI)材料制备的硅基单电子晶体管具有结构可控、工艺可重复的优点。但是,目前单电子晶体管的成品率约为30%,难以满足探测器阵列化的需求。为进一步提高单电子晶体管成品率,首先采用电子束零宽度线曝光工艺精确设定单电子晶体管的图形,其次对感应耦合等离子体刻蚀工艺中的气氛比例进行优化,实现电子束曝光图形的良好转移。最后通过降低氧化温度进一步保持了图形转移的准确度。单电子晶体管的隧穿势垒宽度得到了良好的控制,使成品率提高到90%,增强了单电子晶体管作为阵列化超导太赫兹单光子探测器读出电路的可行性。     

基于单电子晶体管的类双涡卷混沌电路

基于单电子晶体管的特性,利用电流模式技术,提出一种单电子晶体管(SET)的混沌电路实现方法.全SET混沌电路的实现,更加便于用集成电路实现,并降低了工作电压,提高了工作频率带宽.利用SPICE对电路进行仿真,结果验证了电路实现的正确性.     

基于忆阻器-CMOS晶体管的逻辑电路及其应用

针对传统组合逻辑电路存在的硬件资源利用率低和功耗高等问题,提出了一种基于忆阻器和CMOS晶体管的存算一体化组合逻辑电路设计方案。利用忆阻器存算一体、结构简单、与CMOS器件兼容等特性,减少了电路元器件数量。首先利用忆阻器的非易失性和阻变特性,设计忆阻与门、或门,结合CMOS晶体管实现与非门、或非门;然后,利用器件存算一体特性,提出了4R2T结构的异或门及同或门电路;最后,基于忆阻逻辑完备集设计了乘法器电路和图像加密电路,并采用LTspice验证电路功能正确性。结果表明,相比传统电路,所设计的乘法器电路元器件数量减少了50%,具有低功耗特性;所设计的图像加密电路具有良好的加密和解密效果,提升了运算效率。     

CMOS数字集成电路：分析与设计（第三版）（中文版）

内容简介：本书集中讲述CMOS数字集成电路，反映现代技术的发展水平，提供电路设计的最新资料。本书共有15章。前半部分详细讨论MOS晶体管相关特性和工作原理、基本反相器电路设计、组合逻辑电路及时序逻辑电路的结构与工作原理。后半部分介绍应用于先进VLSI芯片设计的动态逻辑电路，先进的半导体存储电路，低功耗MCMOS逻辑电路，双极性晶体管基本原理和BiCMOS数字电路设计，芯片的I／O设计，电路的可制造性设计和可测试性设计等问题。     

基于SET/MOS混合结构的译码器电路的设计

基于SET的I-V特性以及SET与MOS管互补的特性,以MOS管的逻辑电路为设计思想,首先提出了一个SET/MOS混合结构的反相器,进而推出或非门电路,并最终实现了一个唯一地址译码器.通过SET和MOS管两者的混合构建的电路与纯SET实现的电路相比,电路的带负载能力增强;与纯MOS晶体管实现的电路相比,电路同样仅需要单电源供电,且元器件数目得到了减少,电路的静态功耗大大降低.仿真结果验证了电路设计的正确性.     

一种基于互补型单电子晶体管的全加器电路设计

基于单电子晶体管(SET)的I-V特性和CMOS数字电路的设计思想,提出了一种由28个互补型SKT构成的全加器电路结构。该全加器优点为：简化了“P—SET”逻辑块;通过选取一组参数使输入和输出高低电平都接近于0．02mV和0mV,电压兼容性好;延迟时间短,仅为0．24ns。SPICE宏模型仿真结果验证了它的正确性。     

A high-speed four-bit full adder with a resistor coupled Josephson logic

A four-bit full adder circuit implemented in resistor coupled Josephson logic (RCJL) has been designed and successfully tested with 173-ps critical path delay. The full adder circuit uses dual rail logic with emphasis on high-speed operation. An experimental four-bit adder circuit was fabricated using lead-alloy Josephson IC technology with a 5-µm minimum feature size and a 7-µm minimum junction diameter. The circuit consists of 80 devices with 264 junctions. The minimum critical path delay for the ripple carry adder was measured to be 173 ps/4 bits. This result demonstrates the RCJL potential for high-speed digital applications.     

一种静态电路兼容的4GHz 64位动态加法器设计

设计了一个与静态电路兼容的64位动态加法器,采用嵌入逻辑的动态触发器,以及多相位时钟技术,实现了与上、下级静态电路的接口.在加法器内部采用稀疏先行进位策略平衡逻辑路径长度以降低内部负载,提高性能.在STMicro90nmCMOS工艺下,该加法器可工作在4GHz时钟下,功耗45.9mW.     

基于单电子晶体管的数字滤波器硬件实现

基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。在讨论数字滤波器硬件实现原理基础上，由这三个单元电路实现了一个二阶IIR滤波器。SET的SPICE宏模型验证了设计的正确性。     

基于多数决定逻辑非门的低功耗全加器设计

全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。     

DLPA: Discrepant Low PDP 8-Bit Adder

This paper presents a new 8-bit adder circuit, called discrepant low PDP 8-bit adder (DLPA) based on three new full adder cells, which have been designed based on requirements of different positions in each 8-bit adder circuit. In order to design the full adder cells, a new and general method has been proposed aiming to achieve full-swing output and low number of transistors. The proposed adder along with several state-of-the-art adders from the literature have been extensively analyzed and compared together. The results revealed that the power-delay product of DLPA is almost more than 20 % less than that of other compared circuits.     

A parallel full adder circuit using Josephson junctions

Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.     

CMOS ternary dynamic differential logic

A new ternary dynamic differential logic (TDDL) has been developed with some favourable properties: high noise margin, standard CMOS process technology restricted to enhancement p- and n-MOSFETs, and no static power consumption. The complete TDDL circuit for a radix 3 full adder is presented     

A Josephson adder employing high-gain direct-coupled logic gate

A wide-margin adder with a simple configuration employing high-gain direct-coupled logic gates (HDCL's) was studied. A wide-margin half-adder circuit, consisting of a single junction and three HDCL buffer gates, is proposed. In order to obtain a wide-margin circuit, gates were designed to be protective against a noise signal. The experimental circuit fabricated by a conventional Pb alloy Josephson technology with 5-µm minimum line width has shown wide-margin (more than a ± 30-percent bias signal margin) characteristics, as predicted by a computer simulation. This paper also demonstrates that the adder can be simply modified into a wide-margin full adder with a simple configuration by connecting an additional single junction and a buffer gate for a carry signal.     

Proposed low power, high speed adder-based 65-nm Square root circuit

This paper focuses on the design of a 1-bit full adder circuit using Shannon’s theorem and adder-based non-Restoring and Restoring Square Rooter circuits. The proposed adder and Square Rooter schematics were developed using DSCH2 CAD tool, and their layouts were generated with Microwind 3 VLSI CAD tool. The Square Rooter circuits were analysed using standard CMOS 65-nm features with a corresponding voltage of 0.7 V. BSIM 4 was used to analyse the parameters. The proposed adder-based Square Rooter simulated results of the proposed adder with those of CPL, Static Energy Recovery Full (SERF), and CMOS adder cell-based Square Rooter circuits; the proposed adder-based Square Rooter circuit gives better results than the other adder-based Square Rooter circuits. We then compared the results with published results and observed that the proposed adder cell-based Square Rooter circuit dissipates lower power, responds faster, and has a higher EPI and higher throughput.