深亚微米工艺ESD电路设计参数研究

通过器件级仿真来评估ESD保护器件的鲁棒性的方法,对ESD电路的关键设计参数进行了研究.通过器件仿真软件MEDICI对栅极到源极接触孔的距离,栅极到漏极接触孔的距离以及栅极的宽度和长度对ESD性能的影响进行了研究,并分析了它们的失效机理.从而得出经验公式,可以在流片前估算出器件的ESD失效电压.通过在设计阶段预测器件的ESD性能可以缩短设计周期,节约成本.     

40nm狗骨结构对n-MOSFET的性能影响

设计了一组测试结构用来探讨狗骨(dogbone)结构有源区对n-MOSFET性能的影响因素。测试结构和测量数据基于40 nm工艺技术,通过改变狗骨结构有源区的通孔区域到栅极之间的长度(S)来分析对NMOS器件参数如漏端饱和电流、阈值电压和漏电流的影响。实验表明,随着长度S从0.07μm增加到5.02μm,漏端饱和电流和漏电流均先上升后下降,而阈值电压呈单调下降变化趋势。漏端饱和电流和漏电流的趋势表明,狗骨结构有源区主要受到两个因素影响,即沿沟道长度方向的STI应力效应和源极/漏极电阻效应,而源极/漏极电阻效应对S较大的狗骨结构有源区影响更为显著。     

深亚微米ESD保护器件GGNMOS性能分析与设计

本文采用MEDICI作为集成电路ESD保护常用器件—栅极接地NMOS管(GGNMOS)ESD性能分析的仿真工具,综合分析了各种对GGNMOS的ESD性能有影响的因素,如衬底掺杂、栅长、接触孔距离等,为深亚微米下ESD保护器件GGNMOS的设计提供了依据。通过分析发现衬底接触孔到栅极距离对GGNMOS器件ESD性能也有一定影响,此前,对这一因素的讨论较少。最后,根据分析结果,给出了一个符合ESD性能要求的器件设计。     

LDMOS器件静电放电失效原理及防护方法

探讨了LDMOS器件在静电放电脉冲作用下的失效现象和机理,阐述了LDMOS器件受到静电放电脉冲冲击后出现的软击穿现象,和由于寄生npn管导通产生的大电流引起器件局部温度过高,导致金属接触孔熔融的器件二次击穿现象.分析对比了不同栅宽、不同LOCOS长度和埋层结构LDMOS器件的静电放电防护性能.证实了带埋层的深漏极注入双RESURF结构LDMOS器件在静电放电防护方面的显著优势.     

双向可控硅器件在片上静电防护中的应用

设计了一种用于芯片静电放电(ESD)防护的双向可控硅(DDSCR)器件.该器件具有对称性或非对称性骤回I-V特性,可以用于多种应用场合.器件的最优静电防护性能达到94 V/μm.简洁的器件结构用于输入/输出保护,对内部电路的寄生效应小,人体模型ESD测试达到耐压等级3(超过4 kV).在多电源芯片的静电防护中,双向可控硅器件可克服普通器件不能胜任的多模式静电事件的发生.首次提出了双向可控硅器件在高速多媒体接口中静电防护和反向驱动保护的应用.     

一种新颖有源箝位ZVS正激变换器的研究

介绍了一种中心抽头全波整流有源箝位ZVS正激变换器的工作原理及主要参数计算。有源箝位电路由一个箝位开关管和箝位电容组成。变压器磁芯实现无损复位,励磁能量和漏感能量全部传递到负栽.磁芯利用率高,功率开关管承受电压应力降低。通过变压器漏感与开关管输出电容的谐振,主开关管与箝位开关管都可以实现ZVS开通,提高了变换器工作效率。文章首先分析了变换器工作原理,然后给出了主要参数的计算方法,最后通过样机(48V输入5V/20A输出)实验验证了该拓扑的高效性能。     

基于STFOD结构的IC全芯片保护

在具有输入、输出静电保护的集成电路中,往往会出现非正常的静电损伤。这是由电源与地之间的静电压以及管脚之间的静电压通过内部电源线的放电而引起的。这种静电损伤给芯片的制造和使用带来了很大的困难。在基于传输诊测电路的电源到地NMOS ESD保护结构的基础上,设计了基于衬底触发场氧器件(STFOD)结构的箝位电路和版图,使芯片的静电等级得到大幅提高。     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

混合信号IC的ESD保护电路设计

从电路设计的角度,介绍了混合信号IC的输入、输出、电源箝位ESD保护电路.在此基础上,构建了一种混合信号IC全芯片ESD保护电路结构.该结构采用二极管正偏放电模式,以实现在较小的寄生电容情况下达到足够的ESD强度;另外,该结构在任意两个pad间均能形成ESD放电通路,同时将不同的电源域进行了隔离.     

不该省的地方不要省

问:为了节省成本和印刷电路板空间,我可以把放大器内部的ESD二极管用作箝位二极管吗?答:在这个设计中,输入信号会周期性的超出电源电压,所以这位客户希望使用放大器内部的ESD二极管来箝位信号。这个主意听起来不错,实则不然。像其他人一     

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-togate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.     

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.     

The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's

The objective of this paper is to discuss the characteristics of SOI nMOSFET's that can be exploited to clamp HBM ESD stresses and to explain the related failure modes and mechanism observed in these devices. The influence on the HBM ESD protection capability of the first order main parameter: the nMOSFET gate length is investigated. The ESD protection capability for both positive and negative polarity HBM stresses is elaborated and compared. The ESD clamping and device failure mechanisms limiting the ESD protection performance are identified.     

SOI集成电路的ESD保护技术研究进展

近年来，随着SOI技术的快速发展，SOI集成电路的ESD保护已成为一个主要的可靠性设计问题。介绍了SOI ESD保护器件方面的最新进展，阐述了在SOI ESD保护器件设计和优化中出现的新问题，并进行了详细的讨论。     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

部分耗尽SOI ESD保护电路的研究

为了解决SOI技术的ESD问题,我们设计了一种适用于部分耗尽SOI的栅控二极管结构的ESD保护电路,并进行了ESD实验.通过实验研究了SOI顶层硅膜厚度、栅控二极管的沟道长度和沟道宽度,限流电阻以及电火花隙等因素对保护电路抗ESD性能的影响,我们发现综合考虑这些因素,就能够在SOI技术上获得良好的抗ESD性能.     

SCR-based ESD protection in nanometer SOI technologies

This paper introduces an SCR-based ESD protection design for silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are sometimes better known, have long since been used in Bulk CMOS to provide very area efficient, high performance ESD protection for a wide variety of circuit applications. The special physical properties and design of an SOI technology however, renders straightforward implementation of an SCR in such technologies impossible. This paper discusses these difficulties and presents an approach to construct efficient SCR devices in SOI. These devices outperform MOS-based ESD protection devices by about four times, attaining roughly the same performance as diodes. Experimental data from two 65 nm and one 130 nm SOI technologies is presented to support this.     

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime.All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002].The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress.The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.     

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-/spl mu/m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I/sub t2/) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.