SM3算法界面设计及安全性分析

Hash（杂凑）函数是密码学的一个重要分支,广泛应用于消息认证、数据完整性、数字签名等领域。但是随着密码技术的不断发展,特别是王小云教授在2005年美密会上公布了MD5、SHA-1的碰撞实例,证明MD5和SHA-1不安全的。2010年中国国家密码管理局公布了中国商用密码杂凑算法标准-SM3密码杂凑算法,广泛应用于电子认证服务系统。用MATLAB编写出SM3算法程序,并用GUI设计算法界面,界面对于任何输入消息均产生一个杂凑值,并计算所耗时间。实验表明本算法速度快且准确。最后对SM3算法主要攻击方法做了归纳并得出结论：目前SM3算法是安全的。     

一类SHA-x改进杂凑算法的设计及分析

在SHA-1和SHA-2标准算法的基础上,提出一类SHA-x改进杂凑算法的设计。该算法重新设计了杂凑函数Hash值的生成方法,将输出消息摘要的长度从SHA-1的160bit提高到192bit,同时保留了SHA-1模2^32加法的计算特性,以保证整个算法的加密速度。安全性分析表明,新设计的杂凑算法在不过分减慢加密速度的前提下,具有较SHA-1更好的抗攻击能力。     

一种群签名方案的设计与分析

基于椭圆曲线密码系统的优势,设计了一种群签名方案.方案从群签名的初始化、签名过程和验证进行了详细的研究和设计,并且使用了目前最新的杂凑函数SHA-3,增强了签名的安全性.最后分析了该方案的特性,与以基于RSA等通用签名算法进行比较,该方案在效率和安全性方面具有较好的性能.     

一种基于FPGA的可重构密码芯片的设计与实现

介绍了SHA-1、SHA224及SHA256三种安全杂凑算法的基本流程,采用可重构体系结构的设计思想和方法设计出一款可实现这三种算法的可重构密码芯片,并对关键路径进行了优化设计。最后给出了基于Altera公司的Cyclone系列FPGA的可重构密码芯片的实现结果。     

一种基于分组密码的hash函数的安全性分析及构造

利用已有的分组密码构造hash函数是一种非常方便的构造方法.早在1993 年Preneel 等人就对使用分组密码构造的64种hash 函数进行了安全分类,这些hash函数统称为PGV体制,它们都是单倍分组长度的,即输出长度和分组长度相同.2002 年Black在他的论文中对这64 种hash函数的安全性进行了严格的证明,证明其中的20种是安全的,其他是不安全的.随着计算技术的发展,人们感到单倍分组长度的hash函数的安全性不足,于是一些双倍分组长度的基于分组密码的hash函数被提了出来.但是其中的很多是不安全的.在AsiaCrypt2006上,一种使用了5个分组密码的双倍分组长度的hash函数被提了出来.作者声明这种构造方式是安全的,但没有给出安全性证明.本文对该体制进行了分析,发现其安全性并不理想,并针对本文的攻击提出了一种新的基于分组密码的hash函数,同时和SHA-256等hash函数的性能进行了对比.     

S-RFSB算法*

杂凑算法是信息安全领域的常用工具之一。现有杂凑算法的压缩函数多是迭代型的,优点是速度快,缺点是难以进行安全性证明。针对已有算法的基础上进行了研究,并提出了S-RFSB杂凑算法方案。新的方案采用Sponge结构,该结构在运行效率上比传统MD结构高,变换函数设计采用编码理论的困难问题,即伴随式译码问题,变换函数使用矩阵的大小缩小了2b倍。这种密码方案具有抵抗量子计算攻击,可证明安全性,实现速度较快等优点,而且仅涉及简单的矩阵运算。     

基于局部碰撞算法的SHA-1改进算法设计与研究

SHA-1是一种哈希函数,它被广泛使用在电子商务这样的现代安全领域,特别是应用于数据加密通信、数字签名。很多的密码协议、标准中都包括了SHA-1算法,如著名的SSL、IPsec和PKCS。本文通过深入分析SHA-1算法及碰撞算法原理,找出SHA-1算法内部碰撞的原因,对算法中逻辑函数和压缩函数进行改进设计,得到基于局部碰撞算法的SHA-1改进算法。     

单向Hash函数SHA-1的统计分析与算法改进

对SHA-1算法的完备度、雪崩效应度、严格雪崩效应及抗碰撞性进行了逐拍统计分析。针对目前密码学界所揭示出的SHA-1设计缺陷,主要以增强SHA-1算法的非线性扩散特性及抗碰撞性为目标,对其进行改进。改进算法在混合函数中逆序使用改进后的扩展码字序列,并在算法首轮的混合函数中引入整数帐篷映射,加速了差分扩散,改变了原来固定的链接变量传递方式,修正了算法内部结构的设计缺陷。测试与分析结果表明,改进算法提高了非线性扩散程度,增强了算法的安全性。     

Keccak类非线性变换的置换性质研究

Keccak杂凑函数是通过SHA-3最后一轮筛选的五个杂凑函数之一。通过对Keccak杂凑函数的非线性环节进行研究,提出了n元Keccak类非线性变换,并逐比特分析了其变换规律,通过分类研究,给出了两个原象不相等时,象不相等的充分条件和象相等的必要条件;进一步证明了当n为奇数时,n元Keccak类非线性变换是一个置换;当n为偶数时,不是一个置换。最后,证明了当n为奇数时,n元Keccak类非线性变换不是全向置换、全距置换和正形置换,为进一步应用这类编码模型奠定了理论基础。     

一种基于多模式加密算法的文件保护方案*

结合对称密码算法中的DES、IDEA、AES和单向散列算法中的MD5、SHA-1、SHA-256等算法,提出了一种在同一文件内部采用多模式加密的方案,该方案比传统的单一模式加密的方案能更好地保证数据的完整性和安全性.详细描述了该方案的算法实现,通过试验验证了其实用性,同时分析了该方案的优点和不足.     

Cryptographic hash standards: where do we go from here?

Successful attacks against the two most commonly used cryptographic hash functions, MD5 and SHA-1, have triggered a kind of feeding frenzy in the cryptographic community. Many researchers are now working on hash function attacks, and we can expect new results in this area for the next several years. This article discusses the SHA-1 attack and the US National Institute of Standards and Technology's (NIST's) plans for SHA-1 and hash functions in general.     

A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely used—and those expected to be used in the near future—hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase.     

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions’ architectures

Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's utilize hash functions - a special family of cryptographic algorithms. Hardware implementations of cryptographic hash functions provide high performance and increased security. However, potential faults during their normal operation cause significant problems in the authentication procedure. Hence, the on-time detection of errors is of great importance, especially when they are used in security-critical applications, such as military or space. In this paper, two Totally Self-Checking (TSC) designs are introduced for the two most-widely used hash functions: SHA-1 and SHA-256. To the best of authors’ knowledge, there is no previously published work presenting TSC hashing cores. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even erroneous bits, if they are appropriately spread. Additionally, experimental results in terms of frequency, area, throughput, and power consumption are provided. Compared to the corresponding Duplicated with Checking (DWC) architectures, the proposed TSC-based designs are more efficient in terms of area, throughput/area, and power consumption. Specifically, the introduced TSC SHA-1 and SHA-256 cores are more efficient by 16.1% and 20.8% in terms of area and by 17.7% and 23.3% in terms of throughput/area, respectively. Also, compared to the corresponding DWC architectures, the proposed TSC-based designs are on average almost 20% more efficient in terms of power consumption.     

A New Hash Competition

Since the discovery of collision attacks against several well-known cryptographic hash functions in 2004, a rush of new cryptanalytic results cast doubt on the current hash function standards. The relatively new NIST SHA-2 standards aren't yet immediately threatened, but their long-term viability is now in question. The US National Institute of Standards and Technology (NIST) has therefore begun an international competition to select a new SHA-3 standard. This article outlines the competition, its rules, the requirements for the hash function candidates, and the process that NIST will use to select the final winning SHA-3 standard.     

Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs

Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for the implementation of hash algorithms of the secure hash standards SHA-256 and SHA-512 on FPGAs and study their area-performance trade-offs. As several 64-bit adders are needed in SHA-512 hash value computation, new architectures proposed in this paper implement modulo-64 addition as modulo-32, modulo-16 and modulo-8 additions with a view to reduce the chip area. Hash function SHA-512 is implemented in different FPGA families of ALTERA to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to guide a designer to select the most suitable FPGA for an application. In addition, a common architecture is designed for implementing SHA-256 and SHA-512 algorithms.     

BLAKE算法的硬件实现研究

随着对MD5和SHA1攻击方法的提出,美国国家标准技术研究所(NIST)组织启动了SHA-3的征集计划,目前已进入第3轮.BLAKE算法进入了最后一轮竞赛,文中首先综述了BLAKE算法从提交到目前为止在硬件评估方面的状况.在此基础上优化了BLAKE压缩函数在FPGA上实现的关键路径,并在FPGA平台上实现了BLAKE算法.和现有的BLAKE算法在FPGA上实现的吞吐率相比,文中实现结构的吞吐率又有提升.     

High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications

Hash functions are special cryptographic algorithms, which are applied wherever message integrity and authentication are critical. Implementations of these functions are cryptographic primitives widely used in common cryptographic schemes and security protocols such as Internet Protocol Security (IPSec) and Virtual Private Network (VPN). In this paper, a novel FPGA implementation of the Secure Hash Algorithm 1 (SHA-1) is proposed. The proposed architecture exploits the benefits of pipeline and re-timing of execution through pre-computation of intermediate temporal values. Pipeline allows division of the calculation of the hash value in four discreet stages, corresponding to the four required rounds of the algorithm. Re-timing is based on the decomposition of the SHA-1 expression to separate information dependencies and independencies. This allows pre-computation of intermediate temporal values in parallel to the calculation of other independent values. Exploiting the information dependencies, the fundamental operational block of SHA-1 is modified so that maximum operation frequency is increased by 30% approximately with negligible area penalty compared to other academic and commercial implementations. The proposed SHA-1 hash function was prototyped and verified using a XILINX FPGA device. The implementation’s characteristics are compared to alternative implementations proposed by the academia and the industry, which are available in the international IP market. The proposed implementation achieved a throughput that exceeded 2,5 Gbps, which is the highest among all similar IP cores for the targeted XILINX technology.     

Implementation of the SHA-2 Hash Family Standard Using FPGAs

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.     

On security arguments of the second round SHA-3 candidates

In 2007, the US National Institute for Standards and Technology (NIST) announced a call for the design of a new cryptographic hash algorithm in response to vulnerabilities like differential attacks identified in existing hash functions, such as MD5 and SHA-1. NIST received many submissions, 51 of which got accepted to the first round. 14 candidates were left in the second round, out of which five candidates have been recently chosen for the final round. An important criterion in the selection process is the SHA-3 hash function security. We identify two important classes of security arguments for the new designs: (1) the possible reductions of the hash function security to the security of its underlying building blocks and (2) arguments against differential attack on building blocks. In this paper, we compare the state of the art provable security reductions for the second round candidates and review arguments and bounds against classes of differential attacks. We discuss all the SHA-3 candidates at a high functional level, analyze, and summarize the security reduction results and bounds against differential attacks. Additionally, we generalize the well-known proof of collision resistance preservation, such that all SHA-3 candidates with a suffix-free padding are covered.     

可重构散列函数密码芯片的设计与实现

根据不同环境对安全散列算法安全强度的不同要求,采用可重构体系结构的思想和方法,设计一种可重构的散列函数密码芯片。实验结果表明,在Altera Stratix II系列现场可编程门阵列上,SHA-1, SHA-224/256, SHA-384/512的吞吐率分别可达到727.853 Mb/s, 909.816 Mb/s和1.456 Gb/s。