一种可植于软件无线电的低功耗可编程增益放大器

本文提出了一种新的技术,用于优化可编程增益放大器的带宽和功耗的关系。这个可编程增益放大器由三级级联的放大器组成,每一级放大器包括可变增益放大器和直流失调电压消除电路。在消除直流失调的电路中,高通的截止频率可从4 kHz到80 kHz变化。可编程增益放大器芯片使用0.13微米的工艺加工,测试结果表明增益可以从-5dB到60dB连续可调。在 60dB增益模式下,当带宽可从1MHz到10MHz变换,电路消耗的功耗为0.85mA到3.2mA,电源电压为1.2V。它的带内OIP3值为14dBm。     

一种4GHz、23dB CMOS宽带限幅放大器的设计与实现

该文主要介绍了关于宽带限幅放大器在0.18μm CMOS工艺下的设计与实现,该宽带限幅放大器在第二次流片中采用了反比例级联结构、有源电感负载以及添加输出缓冲级技术来保证展宽带宽以及保证整个放大器的稳定性.最后所得测试结果为23dB增益,4GHz 3dB带宽.     

一种10 Gbit/s光接收机前置放大器

基于0.18 μm BiCMOS工艺,设计了一种适用于光纤通信的10 Gbit/s光接收机前置放大器。电路由跨阻放大器、两级可变增益放大器、缓冲器、直流偏移消除电路、峰值探测器和自动增益控制环路组成。跨阻放大器采用并联-并联负反馈结构,在满足增益、带宽要求前提下实现低噪声特性。后级放大器引入了增益可变控制,获得宽输入动态范围,同时采用电容简并技术提升带宽。版图后仿真结果表明,在小信号光电流输入下,放大器的差分跨阻增益为10.7 kΩ,-3 dB带宽为7.4 GHz,平均等效输入噪声电流密度为16.9 pA/Hz。可调增益范围在25.2~80.6 dBΩ内,输入动态范围超过40 dB。在3.3 V电压下,静态功耗为166 mW,版图尺寸为764 μm540 μm。     

0.82～2.2GHz高线性功率驱动放大器设计

用Jazz0.35μmSiGe BiCMOS工艺设计了一个宽带、高线性和增益可调的功率驱动放大器。放大器采用两级级联结构,第一级采用差分结构,双端输入单端输出,第二级采用单端输入单端输出的共发射极放大结构,在3.3V电源电压下,放大器带宽达到0.82-2.2GHz,高增益模式下放大器小信号增益为29.7±1.3dB,低增益模式下小信号增益为19.7±0.9dB,输出1dB压缩点大于13.7dBm,总的直流电流小于20mA。     

一种5.5 GHz 30-dB低成本CMOS宽带限幅放大器

采用0.18 μm CMOS工艺,设计了一种多级级联的差分架构宽带高增益限幅放大器.该限幅放大器是为5 Gb/s同步光纤网络(SONET OC-96)设计的.采用反比例级联结构和低电压降有源电感负载来提高系统带宽,达到了设计目标.仿真结果显示,该限幅放大器获得了约30 dB的增益和5.5 GHz 3 dB带宽,电路功耗为30 m W.     

一种新颖的可应用于多模多频接收机可配置的可变增益放大器

本文阐述了一种新颖的可应用于多模多频接收机射频前端可配置的可变增益放大器的设计方法。可变增益放大器包括增益放大电路,控制电路,直流失调消除电路和模式转换电路四个部分。这种结构可以在保证多模多频应用的前提下通过硬件复用最大化来节省芯片面积和功耗。电路采用0.18 um CMOS 工艺,在1.8V的供电电压下可实现5dB 至87dB的动态范围,电路的带宽（所有增益下）大于80 MHz。此外,直流失调消除电路有效抑制了直流失调成分至小于40mV。整个电路的功耗小于3mA,面积为705um*100um。     

一种5．5GHz 30－dB低成本CMOS宽带限幅放大器

采用0．18μm CMOS工艺，设计了一种多级级联的差分架构宽带高增益限幅放大器。该限幅放大器是为5Gb／s同步光纤网络(SONET OC-96)设计的。采用反比例级联结构和低电压降有源电感负载来提高系统带宽，达到了设计目标。仿真结果显示，该限幅放大器获得了约30dB的增益和5．5GHz3 dB带宽，电路功耗为30mW。     

基于0.18μm CMOS工艺2.5Gb/s宽动态范围光接收机前端放大电路设计

基于0.18μm CMOS工艺设计了适用于2.5Gb/s传输速率的宽动态范围光接收机前端放大电路（包括前置放大器和限幅放大器）.前置放大器采用了RGC输入级的跨阻放大器,并且应用了消直流电路和自动增益控制电路扩展输入动态范围.限幅放大器采用了按比例缩小尺寸、并联峰化和带有有源负反馈的Cherry-Hooper放大器等方法扩展带宽.仿真结果表明：前端放大电路的中频增益为116dBΩ,-3dB带宽为2.13GHz,输入信号动态范围为40dB（0.01～1mA）.     

A 0.8–3GHz RF-VGA with 35dB dynamic range in 0.13μm CMOS* Qin Xi(秦希), Huang Xingli(黄杏丽), Qin Yajie(秦亚杰), Hong Zhiliang(洪志良)?

本文提出了一种使用0.13μm CMOS工艺实现的宽带可变增益放大器（VGA）结构。为了优化该VGA的噪声性能,一个具有15dB固定增益、采用有源反馈结构的预放大器被用来作为第一级,之后采用级联的改进型Cherry-Hooper放大器提供增益调节,双反馈环路在这里被用来扩展Cherry-Hooper放大器的带宽。负容性中和和电容源极退化技术分别被用来进行密勒效应补偿和直流失调取消。测试结果显示,该VGA达到35dB增益调节范围,其高端3dB带宽大于3GHz,在最低增益时,1dB压缩点为-29dBm,在最高增益时,噪声系数达到9dB。该VGA（不包括输出缓冲器）在1.2V电源电压下消耗32mW功率,占用芯片面积为0.48mm₂。     

基于CMOS工艺高速光纤通信系统的限幅放大器

基于CMOS工艺,设计了高速光纤通信系统中的限幅放大器,主要包括四部分:输入缓冲级、输出缓冲级、宽带放大单元和失调电压补偿回路.其中宽带放大单元采用有源反馈技术和并联峰化技术扩展带宽,使限幅放大器的带宽达到6.8GHz,增益为46dB.当输入信号比特率为7Gb/s,输入电压峰峰值在10mV到1V之间波动时,输出摆幅稳定在1.4V.在标准的1.8V电源电压下,整体电路功耗为192.3mW.     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

Fully integrated CMOS limiting amplifier with offset compensation network

A fully integrated CMOS limiting amplifier (LA) is presented. Its novel implementation of the offset compensation circuit completely removes bulky off-chip RC components. The LA is designed using a 0.18 mum CMOS technology and it obtains a 40 dB gain with a bandwidth of 1.8 GHz. The total power consumption is only 18.39 mW under a 1.8 V voltage supply.     

应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器

这篇文章呈现了一个应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器,使用了改进的带负电容抵消技术Cherry-hooper放大器作为增益单元,采用了新颖的电路技术来实现增益调节,该技术在宽带PGA的设计中具有普适性,并且可以大大简化宽带PGA的设计。PGA通过两级增益单元和一级输出BUFFER的级联获得了最大增益30dB和远宽于3GHz的带宽。该PGA集成进整个60GHz无线收发机里面并且用TSMC65nm的CMOS工艺获得实现。整个接收机前端的测试结果表明接收机前端获得了18dB的可变增益范围和>3GHz的带宽,这证明提出的PGA本身获得了18dB的可变增益范围并且带宽是远大于3GHz的。该PGA电源电压为1.2V,功耗为10.7mW,核心版图面积仅仅为0.025mm^2。     

A technique for bandwidth extension and noise optimization of wideband low-noise amplifier with dual feedback loops

A technique for bandwidth extension and noise optimization of wideband low-noise amplifier with dual feedback loops is presented. A LC-ladder matching network has been added in front of conventional amplifier with dual feedback loops. Detailed circuit analysis and general design procedures for the modified amplifier have been provided. The technique is applied to an amplifier covering the frequency range from DC to 6 GHz in a 0.5 μm InGaAs E-mode pHEMT process. Post-layout simulation shows S ₁₁ below ?10 dB, S ₂₂ below ?10 dB, flat S ₂₁ of 16 ± 0.2 dB, and flat NF of 1.85 ± 0.35 dB across the entire band, which confirms the improvement in bandwidth and noise performance.     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

采用噪声抵消技术的无电感宽带低噪声放大器

设计了一款多用途、宽带、无电感的低噪声放大器。放大器的第1级为单端输入差分输出结构,采用了噪声抵消技术来降低噪声;第2级引入有源感性负载,并通过电阻负反馈来扩展带宽。采用TSMC 130 nm工艺对电路进行仿真,后仿结果表明,在0.4~6.2 GHz带宽范围内,S21为19 dB,噪声系数为1.9~2.5 dB,功耗为9.6 mW,电路核心面积为0.08 mm²。     

A 0.18 μm CMOS TIA Plus Limiting Amplifier with a 5.3 GHz Overall Bandwidth for Fiber Optic Communications

A shunt series feedback transimpedance amplifier (TIA), based on a current amplifier using a zero–pole cancellation, followed by a 6 stages limiting amplifier (LA), proves to be suitable as receiver front-end for a 8 Gb/s communications over fiber optic. The front-end is realized with a 0.18 μm CMOS technology, and shows the following performances: the TIA has a 50 dBΩ transimpedance gain and 5.5 GHz bandwidth, the LA has a 46 dB gain and 7.9 GHz bandwidth. The differential voltage swing at the output is 300 mV. The total power consumption is 112 mW.     

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as f_T-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 2³¹–1 with a bit-error rate (BER) of 10⁻¹² at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mV_pp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.     

Fabrication of Transimpedance Amplifier Module and Post‐Amplifier Module for 40 Gb/s Optical Communication Systems

The design and performance of an InGaAs/InP transimpedance amplifier and post amplifier for 40 Gb/s receiver applications are presented. We fabricated the 40 Gb/s transimpedance amplifier and post amplifier using InGaAs/InP heterojunction bipolar transistor (HBT) technology. The developed InGaAs/InP HBTs show a cut‐off frequency (f_T) of 129 GHz and a maximum oscillation frequency (f_max) of 175 GHz. The developed transimpedance amplifier provides a bandwidth of 33.5 GHz and a gain of 40.1 dBΩ. A 40 Gb/s data clean eye with 146 mV amplitude of the transimpedance amplifier module is achieved. The fabricated post amplifier demonstrates a very wide bandwidth of 36 GHz and a gain of 20.2 dB. The post‐amplifier module was fabricated using a Teflon PCB substrate and shows a good eye opening and an output voltage swing above 520 mV.