应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

Ka频段低噪声接收前端设计

介绍了一种应用于卫星通信的Ka频段低噪声接收前端的设计方法.通过合理选择器件组合和电路形式,优化输入连接和电路级间匹配,最终研制完成了Ka频段低噪声接收前端.接收前端的接收信号频率在30 GHz附近.在0.8 GHz工作带宽内,噪声系数小于2.2dB,增益大于60 dB,带内增益波动小于1 dB.3套样机的测试结果验证...     

W波段超外差式辐射计射频前端的设计

针对毫米波辐射计接收前端探测灵敏度低、结构复杂、集成度低的问题,设计了一款用于W波段辐射计的射频前端组件.该组件工作于77～79 GHz频段,采用超外差一次变频接收体制,基于毫米波裸芯片及微带电路技术进行研制,组件集成了低噪声放大、本振源、下变频及中频放大等功能电路.在射频信号输入端,使用厚度为0.127 mm的石英基...     

面向IMT-Advanced应用的射频前端T/R组件的设计与实现

阐述了面向IMT-Advanced应用的射频前端T/R组件中各模块的设计与实现方法,并对接收支路和发射支路进行了设计.宽带开关工作频率范围为0～6 GHz,具有插入损耗低、隔离度高的优点;超宽带低噪声放大器在700 MHz～6 GHz的工作范围内增益高且平坦,噪声系数小;宽带功率放大器采用自适应线性化偏置电路,在5.8 GHz频段具有优良的线性度.整个T/R组件输入电压为5V,接收支路增益为13.75 dB,噪声系数为6.58 dB,发射支路增益为22.77 dB,输出功率为20.2 dBm.     

一种用于软件无线电的接收机射频前端电路设计与实现

设计了一种用于软件无线电的射频前端电路,该电路可工作于短波、超短波频段（3～89MHz）。电路将天线接收的信号经过前端滤波、AGC、放大处理后,将输出信号稳定到2V,直接送给下级进行A/D采样及基带处理。设计的核心是宽带AGC电路,采用了一种级联VGA的形式,较大地提高了AGC电路的动态范围和线性范围。经过硬件实测,该接收电路灵敏度能够达到-90dBm,动态范围为70dB,并且具有线性度高、噪声系数小等特点。     

一种基于HTCC的高隔离度开关电路设计

基于开关芯片实现的开关电路是射频前端的基本单元之一,其功能是实现射频信号的导通和关断,在小功率射频信号传输中应用广泛。本文以6 GHz～15 GHz超宽带、60 dB隔离度为设计目标,采用高温共烧陶瓷基板工艺和级联腔体隔离技术,以级联开关芯片为基本电路结构,设计了高隔离度开关电路。该电路包含一只限幅器和两只吸收式砷化镓单刀单掷开关,装配于两个相邻的隔离腔体结构中,通过类同轴垂直传输过渡到基板内对称带状线传输结构,再辅以两侧地孔,实现电磁屏蔽。对开关电路进行电磁场建模仿真,结果表明该结构具有良好的传输特性和隔离特性;在射频前端电路制造完成后对开关电路进行装配和测试,测试结果与建模仿真结果一致性高,验证了本文设计的开关电路具有高隔离度特性。     

一种应用于GPS射频前端的低噪声混频器

为了克服混频器噪声对GPS接收机灵敏度造成的影响,设计了一种应用于GPS射频前端的低噪声混频器电路.采用自偏置缓冲级放大本振信号,有效地提高了电路性能.该混频器的转换增益为23 dB,噪声系数为4.55 dB,3阶交调点为-9.36 dBm,在1.57 GHz到1.6 GHz频段上,反射系数S11小于-15 dB,电路采用1.8 V电压供电;混频器核心电路静态工作电流1.2 mA,采用CMOS 0.18 μm工艺实现,芯片版图面积为160μm×360μm.     

基于LTCC技术的WLAN射频前端的研制

采用低温共烧陶瓷(LTCC)集成技术,设计和制作了具有立体化新型结构的无线局域网(WLAN)射频前端,并对制得的产品模块进行了测试。结果表明:采用LTCC技术制得的WLAN射频前端的外形尺寸仅为29 mm×18 mm×5 mm,远小于传统同类型WLAN射频前端的尺寸。在2.4～2.5 GHz的工作频率范围内,所制WLAN射频前端的最大输出功率为27 dBm,噪声系数小于1.7 dB,接收增益大于15 dB,发射增益大于20 dB。     

微波低噪声放大器的设计与仿真

低噪声放大器在接收系统中能降低系统的噪声和接收机灵敏度,是接收系统的关键部件。文中按照低噪声放大器电路的设计要求,完成了2GHz基站前端射频低噪声放大器的电路设计,并通过ADS仿真软件对电路进行仿真和优化。最终表明,采用本方案设计的LNA增益约为15dB,噪声系数约为1．2dB,性能稳定,完全达到了通信接收机中对LNA指标的要求。     

一种宽带零中频接收前端的设计

设计了一种宽带零中频解调接收前端,用于实现无人机通信系统高集成度和简化电路方案等。零中频接收前端在925～2 175 MHz载波频段上直接解调10 Mb/s码速率的偏移四相相移键控调制信号,适用于L、S频段的数据传输链路系统。零中频接收电路在10 MHz带宽时,动态增益范围可达到76 dB,射频信号接收灵敏度为-74 dBm。     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

多模式卫星导航接收机中双频段LNA设计

设计出一款应用于多模式卫星导航接收机射频前端的双波段LNA,该电路可以工作在1.575GHz和1.267GHz两个波段附近,覆盖了当今各种卫星导航系统的载波频段.LNA的输入阻抗和输出阻抗均被匹配到50Ω,电路采用0.18μmCMOS工艺实现.测试结果表明该电路在1.575GHz和1.267GHz两个波段上噪声系数分别为0.88dB和0.78dB,功率增益分别为25.5dB和25.9dB,S11分别为-16dB和-12.5dB,1dB压缩点分别为-23.4dBm和-23.6dBm,1.8V供电电压条件下静态工作电流均为4.0mA.电路在上述两个频段上稳定性均满足要求.     

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S_(11) of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

A 24-GHz CMOS front-end

This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.     

A low-power multi-band CMOS RF receiver front-end for ubiquitous sensor network applications

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.