关于VDMOSFET二次击穿现象的分析和研究

在PDP驱动电路中的高压功率器件大量采用了VDMOS器件,由二次击穿引起的器件损坏不容忽视。本文讨论了双极晶体管和功率晶体管VDMOS二次击穿的现象,着重分析了功率晶体管VDMOS二次击穿的原因,并提出了改善其二次击穿现象的最佳设计参数及最优准则：基于寄生晶体管基区结深和浓度优化的方法。同时用器件仿真软件MEDICI模拟了各参数对功率晶体管VDNMOS二次击穿的影响。给出了仿真结果。     

关于塑封VDMOS器件热点的研究

功率VDMOS器件作为新一代高压大电流功率器件兼有双极晶体管和普通MOS器件的优点,广泛应用于各个领域。由于功率VDMOS的工作条件恶劣,在高温大电压的应用环境下失效概率较大。在所有的失效机制中,很大一部分是由于器件无法承受瞬间高压脉冲,致使器件芯片烧坏失效。表现出的是在芯片某处产生一明显的烧穿点即所谓的"热点"。这里主要介绍了塑封VDMOS器件进行单雪崩能量测试过程和实际应用中不良品产生热点的原因,从二次击穿的角度对其进行理论解释并提出一些改进措施。     

功率VDMOS器件的研究与发展

简要介绍了垂直双扩散功率场效应晶体管(VDMOS)的研究现状和发展历史.针对功率VDMOS器件击穿电压和导通电阻之间存在的矛盾,重点介绍了几种新型器件结构(包括沟槽栅VDMOS、超结VDMOS、半超结VDMOS)的工作原理和结构特点,以及其在制造工艺中存在的问题.对不同器件结构的优缺点进行了比较分析.对一些新型衍生结构...     

提高功率晶体管二次击穿耐量的新思路

分析了双极型功率晶体管芯片温度分布与版图设计的相关性，指出版图排不合理导致芯片中区域温度偏高，是诱发二次击穿的一个重要原因。提出了一种提高功率晶体管抗热模式二次击穿耐量的新思路，理论分析与实际应用证明，把发射区安排在基区引线条周边的新设计，可显著改善双极型功率晶体管抗二次击穿特性。     

结构改进的高压VDMOS功率晶体管

本文给出高压VDMOS功率晶体管的一种新颖结构,可以明显地减小器件的导通电阻和保持较高的开关速度。     

高压功率VDMOS管的设计研制

随着功率电子器件进一步向高压、高频、大电流方向发展，VDMOS晶体管的市场将会越来越广阔。通过综合各种模型，优化外延层厚度和掺杂浓度。设计了高压VDMOS器件的元胞图形以及器件尺寸，并在终端利用新的思路，从而提高了漏源击穿电压，基于理论分析在工艺上成功实现了耐压为500V，导通电流为3A的功率VDMOS器件。     

两步扩散发射区功率晶体管芯片上温度分布及抗二次击穿能力的研究

试验研究了采用两步扩散发射区结构的功率晶体管,两步扩散发射区结构在提高芯片上温度分布均匀性和器件抗二次击穿能力方面具有较好的作用.两步扩散发射区器件管芯上的温度分布较一步扩散发射区更为均匀,二次击穿耐量可提高80%以上.     

金槽BSIT：一种新型静态感应晶体管

功率型静态感应晶体管BSIT是一种高频、高速的功率场控制器件,它既具有功率MOS管一样高的开关速度,又具有双极晶体管一样低的导通压降。它不会发生功率MOS管那样的静电击窗,也不会发生双极晶体管那样的二次击穿。它具有很大的过电流能力,有很宽的安全工作区,是一种非常优良的功率开关器件。     

VDMOS器件二维数值模拟和典型参数优化分析

本文编制了功率MOSFET二维稳态分析软件TDSPM程序基于漂移扩散模型,特别考虑了功率器件高压工作状态下的速场特性和强场产生机制,因此可以对器件各工作区(包括击穿区)进行模拟。用全耦合法求解联立方程,用截断法修正迭代结果,大大改善了程序求解的收敛性和稳定性,使求解加压步长可取得很大(饱和区漏压可取100200V)。用TDSPM模拟VDMOS,得到器件的外部特性曲线和内部物理量分布;着重分析了击穿过程的内部机制;最后用TDSPM对器件进行了优化分析。     

国内外大功率晶体管发展动态

本文所指的大功率晶体管是指普通型双极大功率晶体管。包括低频大功率晶体管、功率开关晶体管、高反压晶体管和功率达林顿晶体管四部分。功率场效应晶体管VDMOS、功率晶体管模块GTR、绝缘栅晶体管IGBT、静电感应晶体管SIT、静电感应晶闸管SITH及     

晶体管的新概念

简要介绍了几种晶体管,包括柔性晶体管、单原子晶体管、单电子晶体管、单自旋晶体管、量子力学晶体管、谐振隧穿晶体管、薄膜晶体管、透明晶体管和纳米晶体管的新概念。     

高性能纵向pnp晶体管的研制

pnp晶体管中由于空穴的迁移率较电子的迁移率低得多,再加上纵向pnp管有比npn管严重得多的基区宽度调变效应,一般情况下,难以使纵向pnp管的性能与npn管的性能相媲美。我们从理论上分析了提高纵向pnp管性能的途径,并设计了一套新的工艺流程。在p型外延材料上研制出了BV_(ceo)≥90V、V_(be)≤0.8V、f_T=900MHz、V_(ces)=0.2V、β=60～150、厄利电压大于150V的纵向pnp晶体管。在P型单晶材料上研制出了BV_(ceo)≥65V、f_T≥560MHz、β=60～150的纵向pnp晶体管。具有这种性能的纵向pnp管目前在国内外还很少见。     

Improving mobility and electrochemical stability of a water-gated polymer field-effect transistor

Water-gated organic transistors have attracted considerable attention in the field of biosensors, thanks to their capability of operating in the aqueous environment typical of biological systems at very low voltages (∼1 V). Some examples have been recently reported in the literature, employing different organic materials as the active semiconducting layer, ranging from small molecules to single crystals. Here we report on water-gated polymer-based organic-field effect devices using poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b]thiophene) (pBTTT) as the active layer. Very promising electronic performances, in terms of mobility and operating voltages are obtained; notably, the charge carrier mobility is in the order of 0.08 cm²/V s, which is of the same order of magnitude of values reported for single-crystal based water-gated devices, and consistent with values reported for solid-state polymer dielectric transistors. Moreover, the pBTTT-based device shows improved electrochemical stability, as compared to previously reported polymer based water-gated devices. Importantly, good functioning of the device is demonstrated also when water is replaced by physiological-like solutions. Critical to the transistors operation, besides the good transport properties of the active material, is the key-role played by alkyl side chains and ordered morphology of the polymer at the interface with the liquid environment, which we highlight here for the first time. Our contribution overall provides a useful step towards the development of bio-organic sensors, with enhanced properties in terms of sensitivity and stability, and for a successful exploitation of organic based field effect transistors in biotic/abiotic interfaces.     

Organic thin-film transistors with bilayer of rubbed and evaporated hydrocarbon-based acene as active layer

We have investigated organic thin-film transistors (OTFTs) with a bilayer of rubbed and evaporated hydrocarbon-based acene 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) as an active layer. Using a rubbing process after spin-coating the C8-BTBT, crystallinity of the C8-BTBT thin film was improved and resultant superior OTFT characteristics were realized. We obtained a field-effect mobility of 1.6 cm²/Vs, a threshold voltage of −8.2 V, an on-off ratio of 10⁶, and a subthreshold swing of 55 mV/decade.     

SiGe HBT的速度优化设计

从理论分析角度介绍了优化SiGe异质结晶体管速度的方法。结合双极晶体管的工艺限制，介绍了SiGeHBT的基本原理，讨论了SiGeHBT的发射区／基区／集电区设计。最后，以一个100GHzfmax和fT的HBT为例，对电路制作工艺参数进行了讨论。     

双极模式静电感应晶体管及其复合管的原理

静电感应器件通过控制漏和栅的电压来改变沟道中的势垒高度,从而控制来自源区的多数载流子量,并通过静电式控制沟道中的电势分布,来控制电流。本文说明了BSIT单管及大电流高增益复合管的主要工艺过程和工作原理,特别是BSIT由小电流区域变到大电流区域的过程中Ⅰ-Ⅴ曲线的变化及机理。为了更好地了解BSIT的工作原理,针对DX421型BSIT器件作了计算机模拟,最后对其单管和大电流高增益复合管的一些参数如电流放大系数、阻断电压和饱和压降进行了讨论。     

SiGe异质结微波功率晶体管

本文述评了SiGe异质结微波功率晶体管的特性、结构、工艺及研究进展。     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

基于Z参数的微波晶体管高频噪声网络分析方法

For high-capacity wavelength division multiplexing(WDM) in optical fiber transmission systems, multi-wavelength light sources are needed to be operated at precisely-determined wavelength swith a fine separation of 0.8 or 1.6nm.Increasing efforts have been put into deve...     

用V—MOS管改进行输出电路

本文给出了用V-MOS管代替双极型晶体管作行输出管的实用电路,并且从热损耗和截止损耗出发分析了这种电路的优越性。