基于Sklansky结构的24位并行前缀加法器的设计与实现

针对串行进位加法器存在的延时问题,采用一种基于Sklansky结构的并行前缀加法器,通过对并行前缀加法器各个模块进行优化,设计实现了一个24位并行前缀加法器。通过与24位串行进位加法器进行延时比较,结果表明,Sklansky并行前缀结构的加法器,能有效提高运算速度。     

基于逻辑结构的超前进位加法器的设计

通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。     

基于流水线的自检测进位相关和加法器设计

文章提出了一种基于流水线设计的具有自检测功能的进位相关和加法器。该加法器包括四个8位进位相关和加法器（CDSA）．一个4位超前进位单元（BLCU）和一个奇偶校验器。与普通的行波进位加法器相比，文章设计的加法器硬件实现面积仅增加3．85％，而在关键路径的延时上，该加法器要减少39．2％。     

三值绝热多米诺加法器开关级设计

通过对绝热多米诺电路和加法器的研究,该文提出一种新颖低功耗三值加法器的开关级设计方案。该方案首先利用开关-信号理论,结合绝热多米诺电路结构特点,推导出三值加法器本位和电路与进位电路的开关级结构式,由此得到一位三值加法器单元电路;然后通过单元电路的级联得到四位三值绝热多米诺加法器;最后,利用Spice软件对所设计的电路进行模拟,结果显示所设计的四位三值绝热多米诺加法器具有正确的逻辑功能,与四位常规多米诺三值加法器相比,能耗节省约61%。     

用VHDL设计快速BCD码加法器

介绍了一种多位BCD码快速加法器的设计方法,并给出了3位BCD码加法器的VHDL源程序和在Foundation Series3.1i环境中的模拟结果。     

基于并行前缀结构的十进制加法器设计

针对硬件实现BCD码十进制加法需要处理无效码的问题,设计了一种基于并行前缀结构的十进制加法器。该十进制加法器依据预先加6,配合二进制加法求中间和,然后再减6修正的算法,并将减6修正步骤整合到重新设计的减6修正进位选择加法器中,充分利用并行前缀结构大幅提高了电路运算的并行度。采用Verilog HDL对加法器进行实现并利用Design Compiler进行综合,得到设计的32位,64位,128位的十进制加法器的延时分别为0.56 ns,0.61 ns,0.71 ns,面积分别为1 310 μm2,2 681 μm2,5 485 μm2。     

64位超前进位对数加法器的设计与优化

设计一个应用于高性能微处理器的快速64位超前进位对数加法器.通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路.该加法器采用SMIC 0.18 μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能.     

一种三级流水线加法器设计

加法器是最基本的运算单元,决定了运算单元的速度。论文对一种采用流水线结构的12位加法器进行设计,提出了设计结构,进行电路仿真,最终采用CSMC0.6um数字工艺进行硬件综合,并采用Encounter进行布局布线等后端设计,最终得到整个加法器的物理版图。     

一种高速低功耗MOS电流模逻辑加法器的设计

对具有不同输入端的MOS电流模逻辑(MCML)门电路进行了设计分析,应用MCML单元逻辑电路,设计了一个4位超前进位加法器.基于SMIC 0.13 μm CMOS工艺平台,对设计的加法器进行仿真.结果表明,该加法器的延迟比传统CMOS电路小,可广泛用于高速低功耗逻辑运算单元.     

32位DSP加法器部件的研究与设计

加法器在微处理器数据通路中的应用非常广泛，它的速度也是影响系统性能的关键之一，本文参考了现有的几种典型的加法器原理和结构，针对预研课题某DSP处理器的性能要求，设计了两种超前进位结构加法器，在EP1C20芯片上进行综合并对比各项参数，找出了适合的40位的超前进位加法器设计方案。     

An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit

This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and compact multi-output carry look-ahead (CLA) circuit and a very simple select circuit. Comparisons with other representative 32-bit CSAs show that the proposed adder reduces the area by between 25 and 16%, the number of transistors by between 43 and 30%, and the dynamic power supply between 35 and 16%, while maintaining a high speed.     

基于DSP处理器的加法器的设计

从延迟、功耗、面积等方面对加法器的实现方式性能的比较，适应兼容TMS320C54XDSP处理器的高速、低功耗的需要和结构特点，而采用超前进位加法器的两种设计方案，通过两种方案性能对比和结果分析，最终采用4位一组的分组结构．完成了DSP处理器的40位加法器的设计。     

一种适合VLSI实现的快速加法器

本文提出一种规整结构超前进位加法器,其加法时间与位数的对数成比例;而且其结构规整、逻辑简单、互连容易。SPICE模拟表明,采用2μm CMOS工艺的16位加法器最坏情况延时为5.4ns,并具有位数加倍延时仅增加1.2ns的扩展特性。它可以方便地用全定制或半定制等VLSI设计方法实现。     

Self-timed pipelining using latest arriving signal detection

A self-timed pipelining methodology using latest arriving signal detection is presented. The self-timing control block in the algorithm consists of a self-timing signal generator and pipelining latches. The computation completion of a logic block can be detected and the data latched by the pulse-type self-timing signal for further processing. Using the algorithm, a 32-bit carry look-ahead adder is implemented. Simulation results show that the adder can operate at 800 MHz in 0.25 μm CMOS technology     

Variants of an improved m-valued carry look-ahead adder

An improved m-valued carry look-ahead adder has been described by Manzoul et al. It is based on Ling's type of binary adder. Ling's adder is faster and less expensive than the conventional carry look-ahead binary adder. In this paper, the concept of Ling's approach is explained with a map-method first. Then a few improved m-valued carry look-ahead adders are proposed.     

Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency

The modern portable devices exhibiting multimedia applications demand higher energy efficient signal processing due to limited battery size. The approximate adders have shown a remarkable energy-efficiency over the accurate adders for error tolerant applications. In this paper, three novel approximate carry look-ahead adder (ACLA) architectures are proposed. These approximate ACLAs are achieved by simplifying the Boolean expression of carry generation logic such that the probability of error is small while eliminating number of logic gates. Further, a novel accuracy reconfigurable CLA (Re-CLA) that provides desired quality/accuracy in the given energy budget is proposed. The post layout synthesis results using Synopsys IC Compiler of the proposed adders are computed and analysed against the existing adders. These results demonstrate 37.67%, 18.21%, 18.14% and 15.92% reduction in energy consumption by the proposed 8-bit ACLA-I, -II, -III and -IV adders respectively over the existing approximate adder. Further, the proposed 8-bit and 16-bit Re-CLAs require only 1.92% and 7.08% more energy over the existing CLA for achieving accuracy reconfigurability. Finally, the synthesis results of the Gaussian smoothing filters embedded with the proposed adders show higher energy efficiency with acceptable image quality over the state-of-the-art adder architectures.

     

Faster parallel multiplier

Realization of a parallel multiplier has been considered in a paper by Dadda [1] who has proposed various schemes to get the product using (3, 2), (2, 2) counters, and carry look-ahead adders. The complexity of the carry look-ahead adder in terms of number of two-input gates increases with the length of the adder which in effect reduces the speed. This letter presents an approach that reduces the length of carry look-ahead adder, thus increasing the computation speed with a reduction in logic complexity.     

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-nslatency

Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way set-associative cache. This address adder avoids time-consuming carry propagation by using an A+B=K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-μm process, This wave pipelined RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access