基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

DSP中低功耗全加器的改进设计

在充分研究现有典型全加器结构的基础上,提出了一种结合传输管逻辑和传输门逻辑特点的新型全加器。该全加器采用对称的XOR/XNOR结构,减少了电路延迟,降低了功耗。基于0.18μm CMOS工艺,采用HSPICE对电路进行仿真。结果表明,与典型结构全加器相比,提出的全加器在电路功耗和延迟功耗积(PDP)方面的改进分别为22%和27%。     

由RTD构成的MOBILE单元电路研究

对由共振隧穿二极管(RTD)构成的单双稳态转换逻辑单元(MOBILE)电路进行了详细地研究与分析,并结合实际RTD的特性用PSPICE进行了MOBILE单元电路模拟,总结和验证了MOBILE单元电路变化的三条规律,为进一步研究由RTD构成的多种复杂数字电路奠定了基础。     

一种基于忆阻器的可重配置逻辑电路

分析了具有阈值特性的双极性忆阻器模型的阈值电压和高低阻态开关特性,提出了一种基于该模型的可重配置逻辑电路。与基于忆阻器的蕴含逻辑门电路相比,可重配置逻辑电路具备逻辑运算的完备性,在实现“非”、“或”、“与”运算时,运算速度更快、功耗更低。仿真实验验证了电路逻辑功能的正确性,为设计运算速度更快、功耗更低的全加器和数选器等逻辑电路提供了参考。     

一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路.BDD器件以电流模式的开关电流存储器为基本单元,具有符合二元判定图的两向通路的特点.用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路.给出了或门、异或门及四位加法器电路的例子,并使用HSPICE仿真器进行了仿真,验证了这种器件及其电路的正确性.     

一种新的高速集成逻辑电路——多元逻辑电路(DYL)

介绍了一种新的高速集成逻辑电路。它不同于常用集成逻辑电路那样基于一种基本单元门电路,而是由几种基本单元组合而成所需的逻辑系统,因而并不要求每种基本单元都有阈值特性。其主要基本单元就是一种高速线性“与或”门,工艺很简单。用较粗尺寸工艺试作的四位全加器进位链样品,实测速度为每级进位上升边延迟1ns,下降边延迟更小。每门最大功耗12.5mw。文中还与几种原有的集成辑逻电路进行了分析比较。     

一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路．BDD器件以电流模式的开关电流存储器为基本单元，具有符合二元判定图的两向通路的特点．用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路．给出了或门、异或门及四位加法器电路的例子，并使用HSPICE仿真器进行了仿真，验证了这种器件及其电路的正确性．     

基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件,在数字逻辑电路中具有良好的应用前景。目前,基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究,其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块,设计了一个2位二进制乘法器电路,另一种是结合新型的比例逻辑,即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较,并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器),相比于过去的忆阻乘法器,减少了大量晶体管的使用。     

一种适用于门级网表的混合式静态功耗优化方法

进入深亚微米集成电路设计阶段,静态功耗所占整体功耗的比例快速增大,使之成为当前设计流程中的关键优化步骤。该文提出一种适用于门级网表的混合式静态功耗优化方法。该方法结合了整数规划和启发式算法,以减小电路时序裕量的方式换取电路静态功耗的改善。整体优化流程从一个满足时序约束的设计开始,首先利用整数规划为网表中的逻辑门单元寻找一个较低静态功耗的最优替换单元;其次结合当前所用门单元和最优替换单元的物理和电学参数,按优先级方式逐层替换电路中所有的逻辑门节点;最后利用启发式方法修复可能出现的最大延时违规情况。整体优化流程将在上述步骤中不断迭代直至无法将现有时序裕量转换为功耗的改善。针对通用测试电路的实验结果表明,采用该方法优化后电路静态功耗平均减小10%以上,最高达26%;与其它方法相比,该方法不仅大幅降低了功耗,而且避免了优化后电路最大延时的过度恶化,其最大延时违反量小于5 ps。     

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路——单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型     

Novel pipeline architectures based on Negative Differential Resistance devices

Devices exhibiting Negative Differential Resistance (NDR) in their I–V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.     

低电压低功耗全加器的研究设计

采用传输管逻辑和低电压 XOR/XNOR结构 ,设计了一种新型的适用于低电源电压下工作的低功耗高速全加器电路。在 1 .8V工作电压下 ,获得了运算时间为 0 .85 lns,平均功耗 ( 5 0 MHz) 3.35 μW的良好特性。     

共振隧穿器件应用电路概述——共振隧穿器件讲座(2)

在“共振隧穿器件概述”的基础上,对共振隧穿器件应用电路作了全面概括的介绍。首先对共振隧穿器件应用电路的特点、分类和发展趋势作了简述;进一步对由RTDH/EMT构成的单-双稳转换逻辑单元(MOBILE)和以它为基础构成的RTD应用电路,包括柔性逻辑、静态随机存储(SRAM)、神经元、静态分频器等电路的结构、工作原理和逻辑功能等进行了介绍。关于RTD/HEMT构成的更为复杂的电路,如多值逻辑、AD转换器以及RTD光电集成电路等将在本讲座最后部分进行讲解。     

45nm工艺pn混合下拉网络多米诺异或门设计

提出了一种pn混合下拉网络技术,即在多米诺门的下拉网络中混合使用pMOS管和nMOS管来降低电路的功耗并提高电路的性能. 首先,应用此技术设计了多米诺异或门,与标准的n型多米诺异或门相比,新型异或门的静态功耗和动态功耗分别减小了46%和3%. 然后,在此技术的基础上,综合应用多电源电压技术和双阈值技术设计了功耗更低的多米诺异或门,与标准的n型多米诺异或门相比,静态功耗和动态功耗分别减小了82%和21%. 最后分析并确定了4种多米诺异或门的最小漏电流状态和交流噪声容限.     

New modified-majority voter-based efficient QCA digital logic design

ABSTRACT

Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative solution to the limitation of complementary metal oxide semiconductor (CMOS) technology. One of the most attractive fields in QCA is the implementation of configurable digital systems. This article presents a novel multifunctional gate called the modified-majority voter (MMV). The proposed gate works on the explicit interaction of the cell characteristic property for the implementation of digital circuits. This prominent feature of the proposed gate reduces the maximum hardware cost and implements highly efficient QCA structures. To verify the functionality of the proposed gate, some physical proofs, truth table and computational simulation results are performed. These results assured the validity of the existence of the proposed gate. It also dissipates less energy which has been calculated under three separate tunnelling energy levels using the QCAPro tool. To prove the effectiveness of the proposed MMV gate, several optimal irreversible arithmetic circuits such as three-input XOR, half-adder and full-adder are proposed. The modular layouts are verified with the freely available QCADesigner tool version 2.0.3.     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 μm and 90 nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.