2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

5Gb/s 0.25μm CMOS限幅放大器

采用TSMC 0.25μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达50dB,输入动态范围小于5mVpp,最高工作速率可达7Gb/s,均方根抖动小于0.03UI.此外核心电路功耗小于40mW,芯片面积仅为0.70mm×0.70mm.可满足2.5,3.125和5Gb/s三个速率级的光纤通信系统的要求.     

0.18μm CMOS 10Gb/s光接收机限幅放大器

利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm.     

12Gb/s 0.25μm CMOS低功耗1:4分接器

实现了一种能运用于光传输系统SONET OC-192的低功耗单级分接器,其工作速率高达12Gb/s.该电路采用了特征栅长为0.25μm的TSMC混和信号CMOS工艺.所有的电路都采用了源极耦合逻辑,在抑制共模噪声的同时达到尽可能高的工作速率.该分接器具有利用四分之一速率的正交时钟来实现单级分接的特征,减少了分接器器件,降低了功耗.通过在晶圆测试,该芯片在输入12Gb/s长度为231-1伪随机码流时,分接功能正确.芯片面积为0.9mm×0.9mm,在2.5V单电源供电的情况下的典型功耗是210mW.     

Submicrometer all-optical digital memory and integration of nanoscale photonic devices without isolators

In this paper, the authors introduce multibit all-optical memory devices in nanostructured photonic-crystal circuits using only intrinsic nonresonant optical nonlinearities of semiconductors. Introduced devices can record incoming pulses at speeds of 10 Gb/s using power levels less than 1 mW or at speeds approaching 70 Gb/s using power levels of 10 mW. The incoming pulses are recorded in high-contrast digital output levels independent of the input bit format. The devices exhibit tunable gain for fan-out with negligible reflection and low dissipation and can provide signal regeneration, including reshaping and retiming. Separate signal, clock and reset inputs, and memory outputs coexist without any crosstalk. Input, clock, and output operating frequencies can be independently tuned. By simulating the operation of such all-optical memory devices, it is also shown that nanoscale optical devices can be cascaded to construct densely integrated systems without any isolators or amplifiers, even in the presence of reflections.     

Analysis and application of a novel model for estimating powerdissipation of optical interconnections as a function of transmissionbit error rate

This paper proposes a novel model for estimating power dissipation of optical/electrical interconnections as a function of transmission bit error rate. This model is applied to a simplified optoelectronic transmitter and receiver configuration in which a photodetector is directly connected to the decision circuit. It is analytically verified that this configuration can achieve error-free operation with low power under practical operating conditions. A comparison between optical and electrical interconnections based on this simplified configuration is performed. This result shows the interconnection length and bit rate at which optical interconnection is superior in terms of power dissipation to electrical interconnection, Only optical interconnections achieve error-free operation with 40 mW power dissipation at a transmission bit rate of 10 Gb/s and an interconnection length over 7 m     

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10^-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.     

High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

An 8×8 and an expandable 16×16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8×8 LSI and 2.8 W for the expandable 16×16 LSI     

High-speed and low-power operation of a resonant tunneling logicgate MOBILE

High-speed operations up to 35 Gb/s were demonstrated for a resonant tunneling (RT) logic gate monostable-bistable transition logic element (MOBILE). The test circuit consisted of a MOBILE and a DCFL-type output buffer, and it was fabricated using InP-based resonant tunneling diode/HEMT integration technology. This operation bit rate is close to the cutoff frequency of the 0.7-μm gate HEMTs used in the circuit, and was obtained after improvement of the output buffer design. This result indicates the high-speed potential of the MOBILE, though the speed is still limited by the buffer. The power dissipation of the MOBILE was also discussed based on a simple equivalent circuit model of RTDs. This revealed that the power dissipation is as small as 2 mW/gate over a wide range of operation bit rates     

Integrated laser-diode voltage driver for 20-Gb/s optical systemsusing 0.3-μm gate length quantum-well HEMT's

An integrated laser-diode voltage driver (LDVD) making use of enhancement/depletion AlGaAs-GaAs quantum-well high electron mobility transistors (QW HEMTs) with gate lengths of 0.3 μm has been developed. Its large signal bandwidth is 12 GHz. Eye diagrams of the output signal at bit rates up to 8 Gb/s show an opening similar to that of the input signal. Supporting material is given indicating that the LDVD might operate at bit rates up to 20 Gb/s. The maximum output current is over 90 mA; the maximum modulation voltage of 800 mV corresponds to 40-mA modulation current for a laser diode with 20-Ω dynamic resistance. The power consumption is less than 500 mW     

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-/spl mu/m CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL) and low-bandwidth digitally controlled interpolators. To achieve low jitter while maintaining low power consumption, the dual-loop PLL uses two on-chip linear regulators of different bandwidths, one for the core and the other for the interpolator loop. The prototype chip operates from 400 Mb/s to 4 Gb/s with a bit error rate of <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400-mV output swing driving double terminated links.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit insilicon bipolar technology

A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for nonlinear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a -3.6-V supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 2²³-1 pseudorandom bit sequence     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

DC-40 GHz光通信系统用GaAs PHEMT驱动放大器。

利用0.2μmGaAsPHEMT工艺研制了40Gb/s光通信系统中的光调制器驱动放大器。该放大器芯片采用有源偏置的七级分布放大器结构,工作带宽达到40GHz,输入输出反射损耗约-10dB,功率增益14dB,功耗700mW,最大电压输出幅度达到7V。两级芯片级连后,功率增益约27dB,在40Gbit/s速率下得到清晰的眼图。     

1.25 Gb/s低功耗CMOS光接收机限幅放大器

设计并实现了用于光纤用户网和千兆以太网光接收机的限幅放大器。电路采用有源电感负载来拓展带宽、稳定直流工作点 ,通过直接耦合技术来提高增益、降低功耗。测试结果表明 ,在从 5 m Vp- p到 5 0 0 m Vp- p,即40 d B的输入动态范围内 ,在 5 0 Ω负载上的单端输出电压摆幅稳定在 2 80 m Vp- p。在 5 V电源电压下 ,功耗仅为1 30 m W。电路可稳定工作在 1 5 5 Mb/s、62 2 Mb/s、1 .2 5 Gb/s三个速率上。     

A 60-GHz 38-pJ/bit 3.5-Gb/s 90-nm CMOS OOK Digital Radio

A 60-GHz fully integrated bits-in bits-out on–off keying (OOK) digital radio has been designed in a standard 90-nm CMOS process technology. The transmitter provides 2 dBm of output power at a 3.5-Gb/s data rate while consuming 156 mW of dc power, including the on-chip 60-GHz frequency synthesizer. A pulse-shaping filter has been integrated to support high data rates while maintaining spectral efficiency. The receiver performs direct-conversion noncoherent demodulation at data rates up to 3.5 Gb/s while consuming 108 mW of dc power, for a total average transceiver energy consumption of 38 pJ/bit in time division duplex operation. To the best of the authors' knowledge, this is the lowest energy per bit reported to date in the 60-GHz band for fully integrated single-chip CMOS OOK radios.      

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11- μm CMOS

This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid separates the inbound signal from the signal line voltage and current without using a replica driver. It eliminates the need for precise matching between the replica- and main-driver characteristics, enabling a data rate of 20 Gb/s per differential pair, which is the highest reported for bidirectional signaling. The transceiver occupies 1.0² mm and consumes 260 mW at 20 Gb/s with a bit error rate of less than 10^-12. The area and power overhead due to the hybrid are 0.002 mm² and 7 mW, and correspond to 0.2% and 3% of the total transceiver area and power consumption