4H-SiC(004)面双晶衍射摇摆曲线的分析

用X射线双晶衍射法(XRD)对4H-SiC衬底和在该衬底上外延生长的4H-SiC单晶样品(004)面进行测试,在所有样品的测试结果中发现,摇摆曲线主峰左侧160″附近均出现傍肩,并且主峰衍射强度也较低.依据X射线衍射理论对系统射线在测试样品(004)面的衍射峰位展宽进行计算,并对4H-SiC原子结构进行了分析.研究结果证实,摇摆曲线中傍肩的存在与射线源中的Ka2射线参与衍射有关,而相对较低的衍射强度受其(004)面的特殊双层原子结构的影响.     

化学气相沉积4H-SiC同质外延膜的生长及其特征

采用常压化学气相沉积(APCVD)方法在偏向<11-20>晶向8°的p型4H-SiC(0001)Si-面衬底上进行同质外延生长.霍尔测试的结果表明,非有意掺杂的外延膜层导电性为n型.XRD测试显示各个样品只在位于2θ=35.5°附近出现一个谱峰,表明外延膜是SiC单晶.在低温PL谱中,对于在较低温度下外延生长的4H-SiC样品,在1.8～2.4eV范围内出现很宽的谱峰.而在该样品的Raman谱中,也观察到了典型的3C-SiC的特征峰,表明该样品含有立方相SiC的混晶,这与PL谱获得的结果相吻合.     

化学气相沉积4H-SiC同质外延膜的生长及其特征

采用常压化学气相沉积(APCVD)方法在偏向<11-20>晶向8°的p型4H-SiC(0001)Si-面衬底上进行同质外延生长.霍尔测试的结果表明,非有意掺杂的外延膜层导电性为n型.XRD测试显示各个样品只在位于2θ=35.5°附近出现一个谱峰,表明外延膜是SiC单晶.在低温PL谱中,对于在较低温度下外延生长的4H-SiC样品,在1.8～2.4eV范围内出现很宽的谱峰.而在该样品的Raman谱中,也观察到了典型的3C-SiC的特征峰,表明该样品含有立方相SiC的混晶,这与PL谱获得的结果相吻合.     

化学气相沉积4H-SiC同质外延膜的生长及其特征

采用常压化学气相沉积（APCVD）方法在偏向〈1120〉晶向8. 的p型4H-SiC (0001) Si-面衬底上进行同质外延生长. 霍尔测试的结果表明，非有意掺杂的外延膜层导电性为n型. XRD测试显示各个样品只在位于2θ=355. 附近出现一个谱峰，表明外延膜是SiC单晶. 在低温PL谱中，对于在较低温度下外延生长的4H-SiC样品，在1.8～2.4eV范围内出现很宽的谱峰. 而在该样品的Raman谱中，也观察到了典型的3C-SiC的特征峰，表明该样品含有立方相SiC的混晶，这与PL谱获得的结果相吻合.     

改善玻璃衬底上ZnO薄膜特性的方法

利用磁控溅射法在玻璃衬底上淀积铝掺杂氧化锌(AZO)薄膜作为缓冲层,在其上制备了ZnO薄膜。重点研究了AZO薄膜作为缓冲层对玻璃衬底上ZnO薄膜特性的影响。扫描电子显微镜(SEM)图像和X射线衍射(XRD)图谱分析结果表明,玻璃衬底上加入厚度为1μm的AZO缓冲层后,提高了衬底材料和ZnO薄膜之间的晶格匹配程度,有助于增大ZnO薄膜晶粒尺寸,提高其(002)取向择优生长特性、薄膜结晶特性及晶格结构完整性。室温下的透射光谱结果表明玻璃/AZO和玻璃衬底上ZnO薄膜的透光特性没有显著不同。光致发光(PL)谱研究结果表明AZO缓冲层可以有效阻止衬底表面硅原子从ZnO薄膜中"俘获"氧原子,减少ZnO薄膜中的缺陷,改善ZnO薄膜的结晶质量。     

Si衬底上ZnO外延膜结构性质的比较

采用连通式双反应室高温MOCVD系统在Si衬底上外延ZnO薄膜,通过卢瑟福背散射/沟道(RBS/C)及高分辨X射线衍射(HR-XRD)技术对不同衬底条件的ZnO外延膜进行了组分及结构分析,结果表明在采用SiC缓冲层后,Si(111)衬底上ZnO(0002)面衍射峰半高宽明显减小,缺陷密度降低,单晶质量显著变好,c轴方向应变由0.49%变为-0.16%,即由拉应变变为压应变且应变值变小,说明SiC缓冲层可以有效地减小ZnO与Si衬底晶格失配带来的应变,改善外延膜质量,实现Si衬底上单晶ZnO的生长.     

Si衬底上ZnO外延膜结构性质的比较

采用连通式双反应室高温MOCVD系统在Si衬底上外延ZnO薄膜,通过卢瑟福背散射/沟道(RBS/C)及高分辨X射线衍射(HR-XRD)技术对不同衬底条件的ZnO外延膜进行了组分及结构分析,结果表明在采用SiC缓冲层后,Si(111)衬底上ZnO(0002)面衍射峰半高宽明显减小,缺陷密度降低,单晶质量显著变好,c轴方向应变由0.49%变为-0.16%,即由拉应变变为压应变且应变值变小,说明SiC缓冲层可以有效地减小ZnO与Si衬底晶格失配带来的应变,改善外延膜质量,实现Si衬底上单晶ZnO的生长.     

ZnO缓冲层的厚度对HVPE-GaN外延层的影响

为了得到高质量的GaN材料,首先在c面蓝宝石(Al2O3)衬底上射频磁控溅射不同厚度的ZnO缓冲层,然后采用氢化物气相外延(HVPE)法在ZnO缓冲层上生长约5.2μm厚的GaN外延层,研究ZnO缓冲层的厚度对GaN外延层质量的影响。用微分干涉显微镜(DIC)、扫描电子显微镜(SEM)、X射线衍射(XRD)和光致发光(PL)技术研究分析了GaN外延层的表面形貌、结晶质量和光学特性。结果表明,ZnO缓冲层的厚度对GaN外延层的特性有着重要的影响,200 nm厚的ZnO缓冲层最有利于高质量GaN外延层的生长。     

同质缓冲层对ZnO薄膜光学性质的影响

利用射频磁控溅射技术,在单晶硅衬底上生长出高质量(0002)晶面取向的ZnO外延薄膜。通过XRD、AFM、吸收光谱、光致荧光发光谱的实验研究,发现加入适当厚度的、低温生长的ZnO同质缓冲层,可有效降低晶格失配和因热膨胀系数不同引起的晶格畸变。在衬底温度200℃、沉积时间5min的ZnO缓冲层上,以450℃衬底温度溅射ZnO薄膜主层,得到的ZnO样品的晶体结构、表面形貌和光学性质均有较明显的改善。     

长波InAsSb材料的结构特性研究

用熔体外延(ME)法在InAs衬底上生长了InAsSb外延层,用扫描电子显微镜(SEM)观察了样品的横截面,并测量出外延层的厚度达到100μm,用X-射线衍射(XRD)谱研究了InAsSb外延层的结构性质。测量结果表明,InAs/InAs0.023Sb0.977单晶具有相当完美的晶体取向结构及良好的结晶质量,这可能得益于100μm的外延层厚度基本消除了外延层与衬底之间晶格失配的影响。电子探针微分析(EPMA)测量的元素分布图像显示,Sb(锑)元素在外延层中的分布相当均匀。     

无偏角4H-SiC同质外延温场分布系数的仿真及实验研究

采用化学气相沉积(CVD)方法进行碳化硅(4H-SiC)同质外延生长,生长过程中温场分布是决定外延层质量的关键因素。对CVD系统的温场分布进行了仿真研究,并采用无偏角4H-SiC衬底进行同质外延生长实验验证。结果表明,无偏角4H-SiC外延层中的3C-SiC多型体夹杂与生长室温场分布密切相关。实验数据验证了仿真结果,两者的温度分布具有高度一致性,这也证明了仿真数据的有效性。     

采用场板和边缘终端技术的大电流Ni/4H-SiC SBDs

研究了4H-SiC低缺陷密度外延层的制造和Ni/SiC肖特基势垒二极管的正、反向电学特性。采用了偏8°4H-SiC衬底上台阶控制外延方法进行同质外延,外延温度1580℃,最后得到了低缺陷密度的3英寸外延片。采用了原子力显微镜和扫描电子显微镜进行了测试。在外延片上进行的Ni/4H-SiC肖特基势垒二极管的制造,采用了B+离子注入形成的一个非晶区域作为边缘终端,然后使用经过1000℃下退火10min的PECVD生长的SiO2作为场板介质。最终得到的Ni/4H-SiC肖特基势垒二极管的理想因子为1.03,势垒高度为1.6eV,在反向偏压1102V时,漏电流密度只有1.15×10-3A/cm2。在正向压降3.5V时得到了7.47A的大电流输出,特征导通电阻为6.22Ω.cm2。     

p型4H-SiC同质外延有效层厚度

通过化学气相沉积法,采用不同生长工艺在4°偏角4H-SiC衬底上制备p型4H-SiC同质外延片。提出了p型4H-SiC同质外延中有效层厚度的概念,研究发现导致外延有效层厚度减少的直接原因是自掺杂效应的存在。采用傅里叶红外光谱仪(FT-IR)、汞探针电容电压(Hg-CV)和表面缺陷测试仪对p型4H-SiC同质外延片进行表征,讨论了不同工艺对外延有效层厚度的影响。结果表明,采用隔离法和阻挡层法均能提高外延有效层厚度,且掺杂浓度随距表面深度变化斜率值由1.323减小到0.073。然而,阻挡层法斜率值能进一步优化至0.050,是由于有效抑制了外延中固相和气相自掺杂。对比于优化前工艺,采用阻挡层法制备的p型4H-SiC同质外延片厚度不均匀性和表面总缺陷数量处于同一水平,掺杂浓度不均匀性由2.95%改善到2.67%。综上,采用阻挡层法能够制备出高有效层厚度、高一致性和高质量的p型4H-SiC同质外延片。     

Influence of lattice polarity of nitrogen and aluminum doping on 4H-SiC epitaxial layer

We have reinvestigated the characteristics of N and Al doping on 4H-SiC epitaxial layer. It was found that thermally activated process and desorption process are aspects of the mechanism of the N incorporation to which attention should be paid. The process strongly depends on the lattice polarity and C/Si ratio. Thermally activated process dominates the N incorporation of the Si-face under the high C/Si ratio. Under the low C/Si condition, the desorption process dominates the N incorporation of the Si-face. For C-face, the desorption process dominates the N incorporation regardless of the lattice polarity and the C/Si ratio. Concerning Al doping, the desorption process dominates the Al incorporation without reference to the lattice polarity and the C/Si ratio.     

Micropipe and dislocation density reduction in 6H-SiC and 4H-SiC structures grown by liquid phase epitaxy

We investigated silicon carbide (SiC) epitaxial layers grown by liquid phase epitaxy (LPE). The layers were grown on 6H-SiC and 4H-SiC well-oriented (0001) 35 mm diameter commercial wafers as well as on 6H-SiC Lely crystals. A few experiments were also done on off-axis 6H-SiC and 4H-SiC substrates. Layer thickness and growth rate ranged from 0.5 to 50 microns and 0.5 to 10 μm/h, respectively. Layers were investigated by x-ray diffraction, x-ray topography, and selective chemical etching in molten KOH. It was found that dislocation and micropipe density in LPE grown epitaxial layers were significantly reduced compared with the defect densities in the substrates.     

4H-SiC金属-半导体-金属结构紫外探测器的模拟与分析

用MEDICI软件对金属-半导体-金属(MSM)结构4H-SiC紫外(UV)探测器的I-V特性以及光谱响应等特性进行了模拟与分析,并探讨了金属电极的宽度、电极间距以及外延层厚度对探测器响应度的影响.结果表明,室温下该探测器的暗电流线性密度达到10-13A/μm,且在不同电压下光电流至少比暗电流大两个数量级;探测器的光谱响应范围为200~400 nm,在347 nm处响应度达到极大值;增大指宽或者减小指间距可以提高探测器的响应度;当波长小于峰值波长时外延层厚度对探测器的响应度基本没影响,而当波长大于峰值波长时随着外延层厚度的增大探测器的响应度有所增大.     

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.     

氧化后退火技术对SiO2/4H-SiC界面态密度的影响

采用等离子体增强化学气相沉积(PECVD)低温处理和高温快速退火的技术,研究了退火条件对SiO2/4H-SiC界面态密度的影响.在n型4H-SiC外延片上高温干氧氧化50 nm厚的SiO2层并经N2原位退火,随后在PECVD炉中对样品进行350℃退火气氛为PH3,N2O,H2和N2的后退火处理,之后进行高温快速退火,最后制备Al电极4H-SiC MOS电容.I-V和C-V测试结果表明,各样品的氧化层击穿场强均大于9 MV/cm,PH3处理可以降低界面有效负电荷和近界面氧化层陷阱电荷,但PH3处理样品的界面态密度比N2O处理的结果要高.经N2O氛围PECVD后退火样品在距离导带0.2和0.4 eV处的界面态密度分别约为1.7× 1012和4×1011eV-1·cm-2,有望用于SiC MOSFET器件的栅氧处理.     

S波段功率SiC MESFET(芯片)研制

介绍了一种S波段功率SiC MESFET芯片的研制技术。针对SiC材料的特点,对4H-SiC外延材料进行了设计和仿真,同时对Al记忆效应进行了研究,优化了4H-SiC外延生长技术。研究了栅长与沟道厚度纵横比(Lg/a)对短沟道效应和漏极势垒降低效应的影响。采用了凹槽栅结构和体标记电子束直写技术以及热氧化SiO2和SiNx复合钝化层设计等新制备工艺,实现了栅、漏泄漏电流的减小和源、漏击穿电压的提高。测试结果表明,功率SiC MESFET芯片在3.4 GHz频率下脉冲输出功率大于45 W,功率增益8.5 dB,漏极效率40%。测试条件为漏极工作电压48 V,脉宽100μs,占空比10%。     

Drift-free 10-kV, 20-A 4H-SiC PiN diodes

As impressive as the advancement in 4H-SiC material quality has been, 4H-SiC PiN diodes continue to suffer from irreversible, forward-voltage instabilities. In this work, we describe PiN diodes designed to block 10 kV and conduct 20 A at less than 4.5 V, which were fabricated on 4H-SiC PiN epitaxial layers that were grown with an innovative epitaxial process that has been developed specifically to suppress V_F drift. The diodes fabricated on epitaxial layers that implemented this new epitaxy process showed excellent V_F stability, with 86% of the diodes drifting less than 0.1 V during forward current stressing at 10 A (50 A/cm²) for 30 min. However, these improvements in V_F drift come with a cost in blocking yield, as the surface morphology and other crystal defects imparted by the epitaxial process resulted in only 1 of 50 diodes reaching the 10-kV blocking specification. Nevertheless, the remarkable progress in V_F drift yield brings us closer to commercialization of high-power 4H-SiC PiN diodes.