用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法.在保证传统设计目标(如芯片面积、连线长度、延迟等)不被恶化的基础上,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况,进而优化整个电路性能.并将改进的模拟退火算法应用于集成电路的热布局优化,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时,很好地改善了芯片表面的热分配情况.     

基于热叠加模型的叠层3D多芯片组件芯片热布局优化研究

 叠层三维多芯片组件(3D Multi-Chip Module,MCM)芯片的位置布局直接影响其内部温度场分布,进而影响其可靠性.本文研究了叠层3D-MCM内芯片热布局优化问题,目标是降低芯片最高温度、平均芯片温度场.基于热叠加模型并结合热传导公式,选取芯片的温度作为评价指标,确定出用于3D-MCM热布局优化的适应度函数,采用遗传算法对芯片热布局进行优化,得出了最优芯片热布局方案,总结出了可用于指导叠层3D-MCM芯片热布局设计的热布局规则;采用有限元仿真方法,对所得的热布局优化结果进行验证,结果表明热布局优化结果与仿真实验结果一致,本文所提出的基于热叠加模型的MCM热布局优化算法可实现叠层3D-MCM芯片的热布局优化.     

FAME:一个标准单元模式下基于最小割和枚举的快速详细布局算法(英文)

随着制造工艺的快速进步 ,超大规模集成电路的物理设计技术在速度和质量上面临很大挑战 .提出了一个快速详细布局算法以适应这种要求 .算法继承总体布局得到的单元全局最佳位置 ,然后采用局部优化将单元精确定位 .FM最小割和局部枚举方法分别用于优化 y和 x两个方向的连线长度 ,这两个方向的优化在同一迭代过程中交替进行 .另外 ,采用改进的枚举策略加速算法 ,对于有障碍和宏模块情况下的布局也加以讨论 .实例测试结果表明 ,FAME的运行速度比 RITUAL快 4倍 ,并使总连线长度平均减小 5% .     

FAME:一个标准单元模式下基干最小割和枚举的快速详细布局算法

随着制造工艺的快速进步,超大规模集成电路的物理设计技术在速度和质量上面临很大挑战.提出了一个快速详细布局算法以适应这种要求.算法继承总体布局得到的单元全局最佳位置,然后采用局部优化将单元精确定位.FM最小割和局部枚举方法分别用于优化Y和X两个方向的连线长度,这两个方向的优化在同一迭代过程中交替进行.另外,采用改进的枚举策略加速算法,对于有障碍和宏模块情况下的布局也加以讨论.实例测试结果表明,FAME的运行速度比RITUAL快4倍,并使总连线长度平均减小5%.     

一种同时进行资源分配和布局规划的高层次综合算法

随着集成电路的特征尺寸不断缩小,连线延迟成为决定电路性能的主要因素之一,减小连线网络复杂度已成为高层次综合算法的一个重要内容.本文提出了一种同时进行资源分配和布局规划的算法,使用最小割(Min-Cut)算法对已调度的数据依赖图(DFG)进行多路分割,实现了资源分配,同时又把分割的过程对应到Slicing结构的布局规划中.在算法进行过程中可以不断利用前面步骤所提供的布局信息指导资源分配,从而有效的对连线进行优化.针对设计实例进行的实验表明了这种算法的有效性.     

基于Innovus混合放置的布局规划方法优化

随着集成电路后端设计中宏单元数量增多，传统布局规划方法效率低且耗时，而自动布局规划的混合放置(MP)技术存在物理规则违例数量多、电压降大和功耗高等问题。针对传统方式和MP方式的不足，提出了一种优化的MP布局规划方法，通过控制宏单元通道空间和标准单元密度大小、固定边界宏单元位置及脚本修复TSMC芯片集成检查(TCIC)违例的方法解决MP技术存在的问题。研究结果表明，优化的MP方式保留了MP技术的性能、功耗和面积(PPA)优势，且相比于传统方式布线长度优化了28%,时序违例优化了65%,功耗优化了6.09%。该方案可为多宏单元大规模设计的布局规划提供参考。     

0.18 μm CMOS工艺下的互连线延迟和信号完整性分析

随着深亚微米工艺技术条件的应用和芯片工作频率的不断提高 ,芯片互连线越来越成为一个限制芯片性能提高和集成度提高的关键因素 :互连线延迟正逐渐超过器件延迟 ;互连线上信号传输时由于串扰引起的信号完整性问题已成为深亚微米集成电路设计所面临的一个关键问题。文中分析了芯片中器件和互连线的延迟趋势 ,模拟分析了 0 .1 8μm CMOS工艺条件下的信号完整性问题。     

H.264图像解码芯片的布局布线设计

集成电路工艺发展到深亚微米阶段,IC设计向高速、高复杂度方向发展,物理设计也要满足更加严格的要求.布局布线设计成为集成电路设计的一个关键步骤.本文以一个实际设计为例阐述了在集成电路EDA设计工具的辅助下布局布线的具体实现方法,通过对设计结果的分析,解决了布线拥塞、时序收敛以及信号完整性等问题.该芯片最后达到设计预定的性能指标并交付流片.     

双频双系统导航芯片的时钟树分析和设计

在复杂的超大规模高速集成电路设计中,时钟树的综合与优化是芯片后端设计优化时序过程中至关重要的一环,其中时钟树的设计是最关键的部分.以SMIC 0.13 μm工艺双频双系统兼容接收机数字基带导航芯片为例,根据时钟树时序要求和时钟树延迟模型,基于Synopsys的Astro工具,对芯片进行自动时钟树分析和指定时钟树结构分析,设计和优化了时钟树结构.结果表明,利用此方法得到的时钟树结构能取得更优的结果.     

世界集成电路--十年风光世界惊 设计加工两得意

集成电路发展现状 硅集成电路的发展方向是集成度提高、圆片直径增大、特征尺寸减小、互连线层数增多等.迄今为止其遵循的主要规律,即人所共知的Moore定律:每个芯片上的晶体管数每年增加50%,或每3.5年增加4倍;特征尺寸(沟道长度)、门延迟、连线的步径(线宽+间距)每年减小13%.目前国际上已有15个国家(地区)建有160多条8英寸生产线,7个国家(地区)建有1 2英寸生产线.     

Reliability and routability consideration for MCM placement

This paper presents a methodology based on the fuzzy logic approach for the placement of the power dissipating chips on the multichip module substrate. Our methodology considers both thermal distribution and routing length constraints during multichip module placement. In this paper, the main design issue is the coupled placement for reliability and routability. The objective of the coupled placement is to enhance the system performance and reliability by obtaining an optimal cost during multichip module placement. For reliability considerations, the design methodology is addressed on the placement of the power dissipating chips to achieve uniform thermal distribution. The thermal placement analysis is based on the modified fuzzy force-directed placement method. Placement for routability is based on minimizing the total wire length estimated by semi-perimeter method. The placement trade-off between routability and reliability is illustrated by varying a weighting factor. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated with the finite element method.     

Reliability and wireability optimizations for chip placement on multichip modules

The chip placement problem of multichip module (MCM) designs is to map the chips properly to the chip sites on the MCM substrate. Chip placement affects not only the thermal characteristics of an MCM but also routing efficiency, which translates directly into manufacturability, performance, and cost. This paper presents a solution methodology for the optimal placement problem considering both thermal and routing design objectives simultaneously. The coupling is achieved through use of a hybrid-force model that is a combination of the traditional interconnection-force model and a novel thermal-force model. The placement procedure can be used as a design tool to place chips and then determine the tradeoffs which can be made in placing for reliability and wireability. Experiments on five examples including three benchmarks show that the present algorithm yields very high-quality results.     

Multidisciplinary heat generating logic block placement optimization using genetic algorithm

A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared to the case in which only the wiring length is minimized.     

Thermal distribution calculations for block level placement in embedded systems

Reliability is a very important concern for the embedded systems. Thermal distribution has become an important reliability concern for today’s integrated circuits and these circuits are being used increasingly in embedded systems. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on elctromigration reliability and self-heating effects for today’s very deep submicron technology. Hence, it has become necessary to obtain design with uniform temperature distribution to ensure minimum temperature gradient and avoid hot spots across the chip area. This will minimise reliability problems during the operation of the chip. The uniform temperature distribution can be achieved by appropriate placement of circuit blocks during the physical design. In this paper, thermal distribution of single chip embedded system on silicon is discussed. The thermal distribution calculations require evaluation of switching activity factor of circuit blocks. This factor is determined by computing activities of the blocks based on the application software of embedded system.     

IO单元自动排布算法IOAP

提出了一种应用于芯片物理设计过程中IO单元自动排布的新算法。IO单元排布是芯片物理设计过程中长期依赖经验的环节。IO单元排布的优化对布线,电源网格和设计收敛性的优化有很大贡献。文章重点研究边缘IO单元排布,提出了IO单元自动排布算法(IOAP)。此算法及其相关软件直接应用于视频解码芯片和无线传感器网络处理器芯片(已流片成功)的物理设计流程中。结果表明,IOAP有效改善了芯片的电源网格,时序和布线结果,减少了布线努力,提高了设计收敛性。     

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach

Three-dimensional (3D) ICs have the potential to reduce the interconnect delay, but thermal problem becomes one of the most serious challenges. In this paper, we proposed an efficient thermal aware 3D placement algorithm,which takes use of quadratic uniformity modeling approach. In this model, cell distribution and thermal dissipation are integrated and formulated as a quadratic function through discrete cosine transformation (DCT) with wirelength optimization. Quadratic programming method is utilized to solve the unified quadratic objective function. We update the unified cell distribution and thermal dissipation with each step of the iterative placement process. Thermal distribution was considered enough during placement process even when a cell was moved. To save time, two fast methods to reflect thermal change were proposed for thermal distribution computation. The experimental results show our thermal aware 3D placement algorithm is efficient with about 3% reduction in average temperature and 15% in max temperature but a little perturbation on wire length.     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

混合模式下详细布局算法的时延优化策略

在集成电路物理设计中,布局是提升电路时延性能的关键阶段。对混合单元模式的详细布局采取二段式的时延优化策略,以此提高布局质量。在合法化阶段,代价函数中采用增加时延权重因子的方法来调整单元的移动策略,使单元分布更有利于时延。在优化阶段,对关键路径上单元的位置进行评价,试探性地对这些单元进行位置微调,在减少关键路径时延的同时避免对布局产生大的扰动,进一步优化了时延。实验结果表明,二段式时延优化策略能够在线长代价较小的情况下有效地提升电路性能。     

Thermal placement algorithm based on heat conduction analogy

A thermal force-directed placement algorithm, called TFPA, based on heat conduction analogy, is proposed for MCM design. TFPA begins with the transformation of the real substrate with chips into an unbounded substrate with an infinite number of chips. Then, each chip pushes every other chip with a force based on the heat conduction analogy. Thus, each chip will move in the direction of the force until the system achieves equilibrium. TFPA generates high quality placement results and maintains a cooler and uniform thermal profile, by distributing chip powers as evenly as possible. Unlike conventional force-directed algorithms, which might have serious component overlapping problems, TFPA places chips apart and only little or even no overlap occurs. In practice, the initial placements obtained by TFPA are very close to final placements.     

A hybrid optimization approach for chip placement of multi-chip module packaging

The aim of this article is to provide a systematic method to perform optimization design for chip placement of multi-chip module in electronic packaging. Based on the investigation of the structural and thermal characteristics of multi-chip module, the key performance indexes of multi-chip module that include the lowest internal temperature objective, thermal-transfer accuracy, chip placement are analyzed. A hybrid model is presented by using genetic algorithm and response surface methodology for optimization. Furthermore, some design processes for improving the performance are induced. Finally, an example is discussed to apply the method.