应用于片上网络的BCH码的设计与实现

本文对差错控制编码技术在片上网络(NoC)中的应用进行了研究。通过对三种纠错码在纠错能力、码率、面积和功耗等方面的折中,本文设计实现了适用于片上网络通信的BCH码,并给出了仿真结果。最后将BCH码应用在Hermes NoC平台上,成功地实现了一个基于BCH码的交换—交换的NoC差错控制系统。     

片上网络:新一代的片上系统结构

片上系统是使用共享或专用总线作为芯片的通信资源.由于这些总线具有一定的限制,因此扩展性较差,不能满足发展需求.在这种情况下,目前的片内互连结构将成为多核芯片的发展瓶颈.文章介绍了一种新型的片上体系结构(片上网络)来解决未来片上系统中总线所带来的不足.片上网络作为一种新的片上体系结构,可以解决片上系统设计中所带来的各种挑...     

NoC:下一代集成电路主流设计技术

从SoC的定义出发,依据“PC参考系准则”、“十年变革规律”、“半导体技术发展规律”等基本规律,提出并论证了“NoC是下一代集成电路主流设计技术”的观点,概括了NoC基础理论体系的主要研究领域;简要分析了集成电路NoC体系结构领域可能的关键技术。NoC技术从体系结构上彻底解决了SoC的总线结构所固有的三大问题:由于地址空间有限而引起的扩展性问题,由于分时通讯而引起的通讯效率问题,以及由于全局同步而引起的功耗和面积问题。     

基于通讯的NoC设计

近年来，一种全新的集成电路体系结构——Network on Chip（NoC）已经成为徽电子学科研究的热点佃题之一，其核心思想是将计算机网络技术移植到芯片设计中来，从体系结构上彻底解决片上通讯的瓶颈问题。文章提出了一种基于通讯的NoC设计方法，通过监控和协调NoC的网络通讯来获得更好的性能．并总结了实现该设计方法所必须研究的关键技术。     

Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

片上网络拓扑结构的研究

随着SoC体系结构设计复杂度的提高,传统的总线结构已成为IP核之间通信的瓶颈。为了满足大规模集成电路发展对扩展性、能耗、面积、时钟异步、重用性、QoS等方面的需求,新的设计方法—片上网络(NoC)应运而生,它是对原有设计模式的一次革新。本文分析了NoC的技术特点以及在该领域中的关键技术,详细地对NoC中常见的拓扑结构进行了分类研究,并指出了每种拓扑结构中的优点与不足;然后通过分析每种拓扑结构的性能参数,从而对其性能进行综合的比较。     

Delay Optimized Architecture for On-Chip Communication

Networks-on-chip (NoC), a new system on chip (SoC) paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh (2DDgl-Mesh) for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 (a network simulator) and CINSIM (a component based interconnection simulator) under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our architecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.     

Delay Optimized Architecture for On-Chip Communication

Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.     

多通道NAND闪存控制器的硬件实现

本文提出了在一款片上系统(SOC)芯片设计中的多通道NAND闪存控制器实现方案。在对NAND闪存控制器的结构和实现方法的研究上,闪存控制器利用带两个16K字节缓冲器的高效率缓冲管理控制器来管理4个通道,每个通道可以连接4片闪存芯片。控制器内嵌16比特BCH纠错模块,支持AMBAAHB总线与MLC闪存。文中还介绍了行地址计算与快闪存储器存储单元的初始化。结果分析里给出了控制器的仿真波形、功耗分析和综合结果。在一个存储组与一个通道的配置条件下,控制器的实现只需要71K逻辑门。     

接口标记容错路由算法

随着片上系统(SoC)集成度的不断提高,IP核之间的通信故障成为亟待解决的问题,片上网络(NoC)是解决SoC通信问题的有效途径。容错路由算法是NoC设计中的关键技术,对NoC的通信效率有重要影响。在Valiant随机路由算法和源路由算法的基础上,提出了一种接口标记容错路由算法。该算法吸取了Valiant随机路由算法能平衡网络负载、降低拥塞概率的优良性能与源路由算法中路径不需要计算与查找的特点,减小了传输时延,提高了路由器的利用率。     

An interconnection architecture for network-on-chip systems

Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.     

Nios SoC系统中的BCH编解码IP核的设计

在编码理论中,BCH码是一种得到深入研究的循环纠错码。SoC(片上系统)设计是电子设计的发展方向。BCH码的SoC实现方法和传统的多片实现方法相比,在工程上具有便捷、小型化及高速等特点。文中分析了使用SoC设计方法完成BCH编解码的设计思路;给出了BCH编码、Berleka-mp译码以及CPU接口的实现细节;同时给出了重要模块的仿真结果。     

一种高速延时无关片上异步转同步通信接口的设计

该文提出一种可用于多核片上系统和片上网络的快速延时无关异同步通信接口,由在独特运行协议下工作的环形FIFO实现,可在支持多种数据传输协议的前提下,保证数据从异步模块到同步时钟模块的完整高速传输。在0.18 m标准CMOS工艺下,传输接口的延时为792 ps,平均能耗为4.87 pJ/request,可满足多核片上系统和片上网络芯片高速低功耗、鲁棒性强和重用性好的设计要求。     

Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding

Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies within systems that must deliver high levels of reliability and dependability while satisfying other hard constraints such as low energy consumption. By incorporating novel error correcting codes it is possible to protect the NoC communication fabric against transient errors and at the same time lower the energy dissipation. We propose a novel, simple coding scheme called Crosstalk Avoiding Double Error Correction Code (CADEC). Detailed analysis followed by simulations with three commonly used NoC architectures show that CADEC provides significant energy savings compared to previously proposed crosstalk avoiding single error correcting codes and error-detection/retransmission schemes.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

High-Speed Architectures for Parallel Long BCH Encoders

Long Bose–Chaudhuri–Hocquenghen (BCH) codes are used as the outer error correcting codes in the second-generation Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6-dB additional coding gain over Reed–Solomon codes with similar code rate and codeword length in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. High-speed applications of BCH codes require parallel implementation of the encoders. In addition, long BCH encoders suffer from the effect of large fanout. In this paper, three novel architectures are proposed to reduce the achievable minimum clock period for long BCH encoders after the fanout bottleneck has been eliminated. For an (8191, 7684) BCH code, compared to the original 32-parallel BCH encoder architecture without fanout bottleneck, the proposed architectures can achieve a speedup of over 100%.     

High-level customization framework for application-specific NoC architectures

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.     

Bio-inspired fault tolerant network on chip

The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even.     

超高速BCH码解码改进算法研究

为了满足高速光纤通信系统纠错编码(FEC)的要求,本文提出了一种简单的BCH码解码算法,省略了复杂的矩阵运算,除法运算,也避免了难以理解的迭代运算。其编译码速度快、效率高,并针对硬件特点做了一些优化,特别适合于硬件实现。同时,本文提出了并行算法,大大加快了编译码速度。利用可编程器件FPGA实现,仿真结果完全正确,且非常有效。该算法不仅可用于高速光纤通信系统中,也可以用于其他高速通信系统。