针对固态硬盘应用的多通道闪存控制器实现

本文介绍一种基于MLC闪存和AHB总线的高速大容量数据控制系统的硬件实现方法,所提出的闪存控制器实现带8个8K字节缓冲器的高效率缓冲管理控制器来管理8个通道,每个通道可以连接8个闪存芯片。文中还介绍了快闪存储器存储单元的空白检查和交叉存取操作。实验结果证明该固态盘控制器的最高读速度为230．2MB／s,最高写速度为101．9MB／s．最后给出了控制器的综合结果和功耗分析,在24比特BCH纠错与一个通道的配置条件下,控制器的实现需要315K逻辑门。     

Astoria大容量存储控制器加速手机连接

赛普拉斯(Cypress)半导体公司近日推出了一款支持多层单元(MLC)NAND闪存的新型West Bridge外设控制器Astoria.Astoria控制器最高可支持16个MLC NAND闪存设备,而MLC NAND闪存与相同存储密度的单层单元(SLC)NAND闪存相比,其成本降低了三倍.     

行业聚焦

赛普拉斯推出低功耗的新型高速USB控制器系列赛普拉斯半导体公司推出两款低功耗的低成本、高速USB控制器系列。新型控制器采用了赛普拉斯公司的先进工艺技术,动态和静态功耗降低了近50%。由于动态功耗较低,因此,采用这些新型器件的外设能够以USB总线电源为工作电压。低待机电流使便携式USB应用的电池寿命大幅度延长。E Z-U S B N X2L P系列是专为NAND闪存控制应用而设计的,支持常见的8位NAND闪存接口以及512B和2KB的标准NAND页面大小。8个芯片使能引脚允许器件与8个单通道或4个双通道NAND闪存芯片相连。某些功能是可配置的,…     

美光在NAND竞争中独树一帜

美光科技公司于2006年推出了针对手机和其他便携式设备的Managed NADA闪存技术。Man-aged NAND闪存使用了美光公司的多芯片封装(MCP)技术,在一个小型的BGA封装中结合了高速多媒体卡(MMC)控制器和NAND闪存。     

赛普拉斯West Bridge控制器适用于PMP、PND、无线网卡及其它嵌入式应用

赛普拉斯半导体公司推出了一款具备多层单元(MLC)NAND闪存支持能力的新型West Bridge外设控制器,可为设计者采用成本最低、密度最高的闪存存储器提供支持.这款West BridgeAstoria?控制器最高支持16个MLC NAND闪存设备,而MLC NAND闪存与相同存储密度的单层单元(SLC)NAND闪存相比,其成本降低了3倍.     

SSD的现状及发展前景

半导体硬盘SSD(固态硬盘)由NAND闪存、NAND控制器以及用作缓冲存储器的DRAM所构成(见图1)。在SSD中,坏块管理、纠错编码(ECC)及单元调整等处理都由NAND控制器的闪存转换层(FTL)来执行。SSD的性能不仅取决于NAND闪存的性能,而且在很大程度上还会受到NAND控制器算法的影响。因此,在优化NAND控制器的设计时,需要考虑到NAND闪存的特性。本文将基于NAND闪存的器件技术及电路技术,以NAND控制器技术为中心,论述SSD技术的现状和今后的挑战等。     

赛普拉斯新型West Bridge控制器提供层多单元闪存支持能力

赛普拉斯半导体公司日前推出了一款具备多层单元（MLC）NAND闪存支持能力的新型West Bridge外设控制器，可为设计者采用成本最低、密度最高的闪存存储器提供支持。这款West Bridge Astoria控制器最高支持16个MLCNAND闪存设备，而MLCNAND闪存与相同存储密度的单层单元（SLC）NAND闪存相比。其成本降低了三倍。     

三星中国建厂,战略布局先发制人

在战略规划上步步为营的三星,如今在中国建厂进一步显露其称霸半导体产业的雄心。未来三星恐将进一步垄断存储产业的主流市场,而其他闪存芯片企业的跟进之路将更加漫长而艰辛。韩国三星第二个海外NAND Flash芯片生产厂在2012年初通过了韩国政府的审批,2012年4月确定在中国西安设厂,消息一经发布引起了国内半导体产业界的一片关注。据了解,新工厂初期已确定的投资额为70亿美元,主要用于生产NAND Flash芯片,月产能估计为10万片,将于2013年底前开始量产。三星目前在韩国京畿道华城12产线、器兴14产线均有生产NAND Flash芯片,还有一条只生产NAND Flash的16产线。除韩国本土以     

每月新品

ST72681:双核心控制器咨询号:101意法半导体发布一款面向正在快速增长的U盘市场的双核控制器芯片ST72681,它采用一种先进的体系结构,由ST78位微控制器结合一个NAND闪存接口专用的16位每指令单循环快速输入/输出处理器,并嵌入一个MLC     

NVM Express企业级闪存控制器

新闪存控制器系列拥有两个版本：16通道PCIe×4Ge113（89HF16P04AG3）和32通道PCIe×8 Gen3（89HF32P08AG3）。闪存控制器专为完全遵从NVMe标准而设计，该标准针对PCIeSSD定义了最优化的寄存器接口、指令集和功能集，旨在帮助实现基于基于PCIeSSD产品的广泛采用，并提供一个可扩展的接口以实现SSD技术现在和将来的性能潜力。     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.     

Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code

As NAND flash memory fabrication technology scales down to 20 nm and below, the raw bit error rate increases very rapidly and conventional hard-decision based error correction does not provide enough protection. The turbo product code (TPC) based error correction with multi-precision output from NAND flash memory is promising because of high error-correcting performance and flexibility in code construction. In this work, we construct a rate-0.907 (36116, 32768) extended TPC for 2-bit MLC NAND flash memory, and apply the Chase–Pyndiah decoding algorithm. An efficient complexity reduction scheme is also proposed to eliminate redundant computations in the Chase–Pyndiah decoding algorithm. The replica parallel decoding is also employed to lower the error floor. The experimental results that include the effects of flash memory output precision are presented for a simulated flash memory channel.     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Too little, too soon [solid-state flash memories]

This paper discusses the disadvantages of Samsung's new NAND flash-based solid-state disks (SSD), which range in capacity from 4 to 32 GB aimed at notebook, subnotebook, and tablet computers. The NAND flash was developed to replace other storage media, especially those used in mobile products. However, because of its high price relative to hard drives, sales of NAND flash has been disappointing. Compared to Samsung's NAND flash, the read/write speeds on hard disk drives in most notebooks tend to be faster, reaching up to 80 megabytes per minute.