A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pairs generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by spice with TSMC 0.35-μm CMOS technology and operates with a 2.7 V to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

Simplified clock voltage doubler

A simple clock voltage doubler based on the Nakagome charge pump, is described. It prevents the latch-up of the output switch without requiring an extra charge-pump voltage doubler     

一个精确时钟驱动的Dickson倍压电荷泵电路

提出了一种基于Dickson电荷泵电路，由自带参考电压的时钟电路驱动，并与耦合倍压电路相结合的片上升压电路。该电路由于保证了输出编程电压的精确度，从而控制了存储单元阅值电压的偏移，降低了对外围电路的要求，保证了整个系统的可靠性。     

Design of photovoltaic device and DC–DC converter on a single chip using 0.18 μm standard CMOS technology

In this paper, we propose a photovoltaic power supply for a stand-alone system that provides electrical generation and voltage boost functions on a single silicon chip. This power supply consists of solar cells, an oscillator, and a bootstrap charge pump, which are all designed in a 0.18 μm standard complementary metal-oxide semiconductor technology. Two types of solar cells are embedded in the system to improve its power efficiency. One type is used for the power supply and the other type is used to provide the voltage bias. Three different solar cells structures were designed. A pn structure and an np structure are used for the power supply cells and an npn series-connected structure is used for the oscillator circuit to operate the DC–DC converter The voltage-current characteristics of the solar cell under microscopic illumination have been measured and the performance of bootstrap charge pump circuits was confirmed. We remodeled our solar cell equivalent circuit to reflect these measurement results.     

Efficiency improvement in charge pump circuits

Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 mA loading on both inverting and noninverting outputs. The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 kHz. A start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A slow turn-on, fast turn-off driving scheme is used in the clock buffer to reduce power dissipation. The new dual charge pump circuit was fabricated in a 3-μm p-well double-poly single-metal CMOS technology with breakdown voltage of 18 V, the die size is 4.7×4.5 mm². For comparison, a charge pump circuit with conventional level shifter and clock buffer was also fabricated. The measured results show that the new charge pump has two advantages: (1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500 Ω and (2) the breakdown voltage requirement is reduced from 19.2 to 17 V     

Power delay optimization of nanoscale 4×1 multiplexer using CMOS based voltage doubler circuit

This paper represents a low leakage, highly efficient and delay improved 4×1 MUX with MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration with nanoscale structure. The unique newly designed voltage doubler circuit is implemented as an additional circuit at the output of the implemented proposed design to step-up the voltage. It means that the output peak voltage is doubled due to the transient of both positive and negative cycles. This stepped-up voltage may be exploited as a stabilized supply for specific applications. The voltage doubler circuit is not enough to improve the overall performance of proposed 4×1 MUX design. In order to integrate the optimization criterion of leakage power and delay performance, the voltage doubler circuit is utilized along with the MOS configuration of augmented sleep transistors. To minimize the parameter of leakage power dissipation theMOSbased voltage doubler circuit cum augmented sleep transistorsMOSconfiguration is introduced. This will mitigate the redundant unused leakage power dissipation of the circuit. This additional circuitry brings out the aspired level of output voltage for the proposed and implemented 4×1 MUXwith better performance parameters. The whole simulation has been done for the 45nmtechnology. It is finally summarized that the leakage power dissipation is minimized up to 55% just around and the delay performance is also improved up to a desired level due to the utilization of MOS based voltage doubler circuit with the MOS configuration of augmented sleep transistors. In this paper, different combinations of MOS based augmented voltage doubler circuit implemented at the output of 4×1 MUX are represented.     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

低抖动的480 MHz CMOS电荷泵式锁相环

本文设计了一款用于USB2.0时钟发生作用的低抖动、低功耗电荷泵式锁相环电路。其电路结构包含鉴频/鉴相器、电荷泵、环路滤波器、压控振荡器和分频器。电路设计是基于CSM0.18μmCMOS工艺,经HSPICE仿真表明,锁相环输出480MHz时钟的峰峰值抖动仅为5.01ps,功耗仅为8.3mW。     

双模式高集成负电荷泵电路设计

提出了一种新颖的双模式高集成开关电容电荷泵。该电荷泵集成高频振荡器、电平移位、逻辑驱动以及4个功率MOSFET开关。与传统电荷泵相比,该电路可以工作在单电源以及双电源两种模式。单电源模式下,输出电压为-VCC;双电源模式下,输出电压为-3×VCC。电路采用0.35μm BCD工艺实现。测试结果表明:室温时,单电源模式和双电源模式下电荷泵输出电流分别为36 mA和80 mA时输出电压分别为-3.07 V和-12.10 V。在-55℃到125℃温度范围内,单电源模式和双电源模式下电荷泵输出电流分别为24 mA和50 mA时输出电压分别低于-3.06 V和-12.35 V。该电荷泵在两种模式下工作特性良好,已应用于相关工程项目。     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

一种适用于MEMS麦克风的新型恒压电荷泵设计

实现了一种新型恒压输出电荷泵电路,通过选择合理的电荷泵结构能有效抑制反向电流及衬底电流,并通过一种负反馈稳压电路得到低纹波且不随电源电压变化的稳压输出,非常适用于MEMS麦克风。该电路采用MIXIC0.35μm标准CMOS工艺实现,测试结果表明该电路能自适应2.8～3.6V的电源电压变化,输出稳定的9V直流电压。     

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

一种用于LED驱动的高效电荷泵电路的设计

设计了一种用于LED驱动的高效1.33X/1.5X/2X电荷泵电路,可以根据输出电压的变化,自适应地切换工作模式。以提高电荷泵的转换效率为切入点,从降低电荷泵升压倍数和减小电荷泵自身功耗两个方面对电荷泵的效率进行了优化设计。从仿真与测试结果可以看出,1.33X模式的转换效率比传统的1.5X模式提高了10%左右,最高效率可达86%。     

新型全差分电荷泵设计

采用差分输入和差分输出方案，设计了一种新型的全差分电荷泵。采用差分输出不仅能够降低电荷泄满所带来的电压噪声，而且能够提高电荷泵的上升和下降速度，从而提高锁相环的工作速度，还能增大输出电压的范围。在差分输入端，采用正反馈电路结构，以提高开启和关断速度，并降低功耗。上拉泵电路和下拉泵电路完全对称，能够消除电流失配所带来的噪声。     

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

Charge pump design for high-voltage biasing applications in piezoelectric-based miniaturized robots

Fully autonomous piezoelectric-based miniaturized robots usually have a high-voltage biasing system that provides the required voltage levels to drive properly their piezoelectric actuators. In this paper a novel on-board biasing system based on the cascade connection of three full-custom charge pump ICs is presented. Simulated and experimental results show that the proposed biasing system is capable to obtain a regulated output voltage up to 20 V from a 3.3 V battery and deliver successfully up to 120 mW of power. Moreover, a novel approach in the steady-state analysis of the two-phase voltage doubler (which is the core of the designed charge pump IC) has been developed in order to have a tool capable to provide a full understanding of the steady-state voltage doubler’s behavior while at the same time accelerate and simplify the design process of such circuit. Simulated results show that the proposed mathematical model is more accurate than already developed models. The design of the charge pump IC has been implemented using a commercial 0.7 μm Bipolar-CMOS-DMOS (BCD) technology.     

一种用于TDC的低功耗多相时钟生成电路北大核心

在无人机3D地形测绘中，作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量，文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器，通过优化交叉耦合结构，在保证低功耗的前提下，提升了信号边缘的斜率，增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中，通过对环路带宽的考量选取了极低的偏置电流，在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明，在400 MHz的输出频率下，环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度，相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。     

DC-DC电荷泵的研究与设计

以Dickson电荷泵的基本原理为出发点，研究了一种将正电压输入转为负电压输出的开关电容电路。由于开关电容的充放电特点，为确定电容时间常数，采用非交叠时钟控制信号避免了由于时钟交叠而造成的当电容充电还未完成即对下一级电容进行放电的现象。同时，参考功率MOS-FET的电容模型通过增大驱动电路的电流减小了开关管的上升延时，提高了开关动作的速度，使转换效率得到明显提高。此电路结构简单，性能优良，易于集成，可广泛应用于输出负电压的电源产品中。     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.