湿法腐蚀研究PVT法生长的SiC单晶中的位错

采用湿法腐蚀对不同电阻率的4H-SiC衬底进行腐蚀。观察发现,对于同一类型缺陷,低电阻率衬底的缺陷腐蚀坑尺寸比高电阻率衬底的小1~2倍,证明氮元素掺杂的低电阻率SiC衬底的腐蚀速率更低。通过显微镜观察腐蚀后的衬底,对六边形的螺位错(TSD)、近圆形的刃位错(TED)和贝壳形的基平面位错(BPD)腐蚀坑进行了分析。对比了TSD与微管腐蚀坑形貌的区别,虽然两种缺陷腐蚀坑都具有六边形形貌,但微管腐蚀坑尺寸比TSD腐蚀坑大1.4倍左右。通过对位错密度的统计,发现目前4H-SiC衬底中主要的位错为TED和BPD,而TSD密度相对较低,仅为420 cm-2。     

杂质对硅单晶机械性能影响的电子理论研究

根据位错理论建立了Si中纯净及掺杂60°位错模型,利用Recursion方法计算了Si中纯净及掺杂60°位错这种典型环境下的能量和电子结构,由此得出:N、O杂质在位错区比在非位错区更稳定,且O优先偏聚于位错,不过当O含量不高时,N、O可以同时偏聚于位错;在位错芯处原子除受近邻Si原子的作用外,还要受到杂质原子的钉扎作用,且N 的这种作用比O强,这就从电子理论上解释了掺杂适量的氮可以提高Si的强度和抗翘曲度的事实.     

杂质对硅单晶机械性能影响的电子理论研究

根据位错理论建立了Si中纯净及掺杂60°位错模型,利用Recursion方法计算了Si中纯净及掺杂60°位错这种典型环境下的能量和电子结构,由此得出:N、O杂质在位错区比在非位错区更稳定,且O优先偏聚于位错,不过当O含量不高时,N、O可以同时偏聚于位错;在位错芯处原子除受近邻Si原子的作用外,还要受到杂质原子的钉扎作用,且N 的这种作用比O强,这就从电子理论上解释了掺杂适量的氮可以提高Si的强度和抗翘曲度的事实.     

半导体技术

O472005040261半导体氮化铟(InN)的电学性质/潘葳,沈文忠,郭其新(上海交通大学物理系凝聚态光谱与光电子物理实验室)//物理学进展.―2004,24(2).―195～215.该文总结了近年来半导体InN薄膜材料(主要是六方纤锌矿结构的InN及异质结构)的电学性质研究进展,重点内容为InN的载流子浓度和迁移率造成InN中高电子浓度现象的施主分析、载流子输运特性及表面、界面特性等.同时也涉及了部分立方闪锌矿结构InN的电学特性和InN在器件(主要是高电子迁移率晶体管器件)上的潜在应用.图20表0参79O472005040262Si/Si直接键合界面的FTIR和XPS研究/陈…     

半导体锗中60°棱位错的电子结构

本文依据位错的弹性理论建立了半导体锗中 6 0°棱位错模型 ,用Recursion方法计算包含与不包含位错时原子团平均态密度、位错芯及其近邻原子的局域态密度、轨道电子数及原子价 ,得出了锗中 6 0°棱位错附近的局域电子结构 ,并讨论了其对锗光学和电学性质的影响。     

Si衬底MOCVD生长GaN/InGaN多量子阱缺陷TEM研究

用透射电子显微镜对Si衬底生长GaN/InGaN多量子阱材料进行横断面测试,在衬底和缓冲层区域进行高分辨电子显微成像(HRTEM)、电子衍射衬度成像、选区电子衍射成像,在量子阱附近区域进行了双束近似电子衍衬像对其位错特性进行研究;用场发射扫描电子显微镜对饱和KoH溶液腐蚀前后材料成像.结果发现,AIN缓冲层具有多孔结构,高温GaN层位错平均密度达108cm-2,同扫描电子显微镜得到的六角腐蚀坑密度一致,量子阱以下发现大量位错发生90°弯曲,而使穿过量子阱位错密度大大降低.在线位错中,以刃位错居多,其次是混合位错,所观察区域几乎未见螺位错.     

可用于Ⅲ族氮化物生长的50mm 3C-SiC/Si(111)衬底的制备

利用新研制出的垂直式低压CVD(L PCVD) Si C生长系统,获得了高质量的5 0 mm 3C- Si C/ Si(111)衬底材料.系统研究了3C- Si C的n型和p型原位掺杂技术,获得了生长速率和表面形貌对反应气体中Si H4 流量和C/ Si原子比率的依赖关系.利用Hall测试技术、非接触式方块电阻测试方法和SIMS,分别研究了3C- Si C的电学特性、均匀性和故意调制掺杂的N浓度纵向分布.利用MBE方法,在原生长的5 0 mm 3C- Si C/ Si(111)衬底上进行了Ga N的外延生长,并研究了Ga N材料的表面、结构和光学特性.结果表明3C- Si C是一种适合于高质量无裂纹Ga N外延生长的衬底或缓冲材料.     

Si衬底MOCVD生长GaN/InGaN多量子阱缺陷TEM研究

用透射电子显微镜对Si衬底生长GaN/InGaN多量子阱材料进行横断面测试,在衬底和缓冲层区域进行高分辨电子显微成像(HRTEM)、电子衍射衬度成像、选区电子衍射成像,在量子阱附近区域进行了双束近似电子衍衬像对其位错特性进行研究;用场发射扫描电子显微镜对饱和KoH溶液腐蚀前后材料成像.结果发现,AIN缓冲层具有多孔结构,高温GaN层位错平均密度达108cm-2,同扫描电子显微镜得到的六角腐蚀坑密度一致,量子阱以下发现大量位错发生90°弯曲,而使穿过量子阱位错密度大大降低.在线位错中,以刃位错居多,其次是混合位错,所观察区域几乎未见螺位错.     

非掺杂LEC砷化镓晶体中砷沉淀和位错关联性质

通过使用激光散射扫描的方法,定性地研究非掺杂半绝缘LEC砷化镓（100）方向生产的晶体中砷沉淀在晶体径向截面分布,得到了在一种特定热场中生长的晶体中存在4个砷沉淀的聚集中心结论,而这4个聚集中心却正好是晶体上位错密度相对较低的区域.作者主要研究了这种分布和位错之间的关系,分析其形成过程,并得出在晶体生长及后期退火过程中,位错在晶体中起到了输送砷原子的管道作用,加速了砷原子在晶体中的扩散过程,导致网格位错密集区的大直径砷沉淀的密度相对位错稀疏区和位错线区的砷沉淀密度较低.     

非掺杂LEC砷化镓晶体中砷沉淀和位错关联性质

通过使用激光散射扫描的方法,定性地研究非掺杂半绝缘LEC砷化镓(100)方向生产的晶体中砷沉淀在晶体径向截面分布,得到了在一种特定热场中生长的晶体中存在4个砷沉淀的聚集中心结论,而这4个聚集中心却正好是晶体上位错密度相对较低的区域.作者主要研究了这种分布和位错之间的关系,分析其形成过程,并得出在晶体生长及后期退火过程中,位错在晶体中起到了输送砷原子的管道作用,加速了砷原子在晶体中的扩散过程,导致网格位错密集区的大直径砷沉淀的密度相对位错稀疏区和位错线区的砷沉淀密度较低.     

腐蚀坑处氮化镓二次MOCVD外延生长的特性

利用熔融KOH液对单层Ga N腐蚀后进行二次MOCVD外延生长,对不同二次生长时间的薄膜及生长前的薄膜进行扫描电子显微、X射线衍射和光致发光测试,实验结果表明二次生长2 h的薄膜具有最低的位错密度和最好的光学特性.在腐蚀坑处,坑中早期的慢速生长及后期的侧向生长都抑制穿透螺位错的生长,坑边缘与中心的非对称生长会引入新的穿透刃位错,莲花状坑结构相遇连通可以使连通处的穿透刃位错消失.     

Dislocation density reduction in GaAs epilayers on Si using strained layer superlattices

Defects such as dislocations and interfaces play a crucial role in the performance of heterostructure devices. The full potential of GaAs on Si heterostructures can only be realized by controlling the defect density. The reduction of threading dislocations by the use of strained layer superlattices has been studied in these heterostructures. Several superlattice structures have been used to reduce the density of threading dislocations in the GaAs epilayer. In this study, we have optimized the use of strained layer superlattices with respect to the position, period and number to reduce and control the dislocation density. The use of strained layer superlattices in conjunction with rapid thermal annealing was found to be a most effective method for reducing the threading dislocation density. Transmission electron microscopy has been used to study the dislocation density reduction and the interaction of threading dislocations with the strained layers. A model has been developed based on energy considerations to determine the critical thickness required for the bending of threading dislocations.     

异质外延GaN中穿透位错对材料发光效率的影响

用阴极射线致发光(CL)法、透射电子显微镜(TEM)和X射线衍射(XRD)法研究了异质外延GaN材料的发光性质与结构特性的关系.结果表明,GaN外延层中的穿透位错是材料有效的非辐射复合中心,但GaN的CL带边峰强度并不随位错密度的增加而减少.两步法生长GaN形成的马赛克结构的亚晶粒尺寸和晶粒间合并产生的位错的弯曲程度是影响材料发光效率的关键.     

Removal of threading dislocations from patterned heteroepitaxial semiconductors by glide to sidewalls

We have shown that threading dislocations can be removed from patterned heteroepitaxial semiconductors by glide to the sidewalls, which is driven by the presence of image forces. In principle, it should be possible to attain highly mismatched heteroepitaxial semiconductors which are completely free from threading dislocations, even though they are not pseudomorphic, by patterned heteroepitaxial processing. There are two basic approaches to patterned heteroepitaxial processing. The first involves selective area growth on a pre-patterned substrate. The second approach involves post-growth patterning followed by annealing. We have developed a quantitative model which predicts that there is a maximum lateral dimension for complete removal of threading dislocations by patterned heteroepitaxy. According to our model, this maximum lateral dimension is proportional to the layer thickness and increases monotonically with the lattice mismatch. For heteroepitaxial materials with greater than 1% lattice mismatch, our model predicts that practical device-sized threading dislocation-free regions may be realized by patterned heteroepitaxial processing.     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.     

MOCVD法侧向外延生长高质量GaN

利用金属有机物气相外延法(MOCVD)，在GaN/蓝宝石复合衬底上，采用侧向外延生长技术制备出高质量的GaN外延膜，并对其进行扫描电镜、X射线双晶衍射、透射电镜测量和分析. 发现完全合并后的GaN外延层的表面平整，晶体质量较衬底有大幅的提高，透射电镜进行微区位错观察发现窗口区穿透位错大部分发生转向，侧向生长区下方的穿透位错被掩膜阻断.     

Low threading dislocation density GaAs on Si(100) with InGaAs/GaAs strained-layer superlattice grown by migration-enhanced epitaxy

This paper reports a promising approach for reducing the density of threading dislocations in GaAs on Si. In _x Ga_1-x As/GaAs strained-layer superlattices (SLSs) grown by migration-enhanced epitaxy at 300° C on GaAs/Si acted as barriers to threading dislocations. Unlike conventional high-temperature-grown SLSs, the low-temperature-grown SLSs were hardly relaxed by the formation of misfit dislocations at GaAs/SLS interfaces, and this allowed them to accumulate considerable strain. New threading dislocation generation due to the misfit dislocation was also suppressed. These factors caused effective bending of threading dislocations and significantly reduced the dislocation density. For the samples that had an SLS withx = 0.3, the average etch-pit density was 7 × 10⁴ cm^-2, which is comparable to that of GaAs substrates.     

GaAs on Si substrate with dislocation filter layers for wafer-scale integration

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-μm bowing was observed using the 725-μm-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4 × 10⁷ cm⁻². For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-μm-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.     

Structural characterization of thick, high-quality epitaxial Ge on Si substrates grown by low-energy plasma-enhanced chemical vapor deposition

In this paper, we report on the growth of epitaxial Ge on a Si substrate by means of low-energy plasma-enhanced chemical vapor deposition (LEPECVD). A Si_1?xGe_x graded buffer layer is used between the silicon substrate and the epitaxial Ge layer to reduce the threading dislocation density resulting from the lattice mismatch between Si and Ge. An advantage of the LEPECVD technique is the high growth rate achievable (on the order of 40 Å/sec), allowing thick SiGe graded buffer layers to be grown faster than by other epitaxial techniques and thereby increasing throughput in order to make such structures more manufacturable. We have achieved relaxed Ge on a silicon substrate with a threading dislocation density of 1 × 10⁵ cm^?2, which is 4?10x lower than previously reported results.     

A novel approach for the complete removal of threading dislocations from ZnSe on GaAs (001)

Here we demonstrate a novel approach to the complete removal of threading dislocations in ZnSe on GaAs (001). This approach, which we call patterned heteroepitaxial processing (PHP), involves post-growth patterning and thermal annealing. Eyitaxial layers of ZnSe on GaAs (001) were grown to thicknesses of 2000–6000 A by photoassisted metalorganic vapor phase epitaxy (MOVPE). Following growth, layers were patterned by photolithography and then annealed at elevated temperatures under flowing hydrogen. Threading dislocation densities were determined using a bromine/methanol etch followed by microscopic evaluation of the resulting etch pit densities. We found that as-grown layers contained more than 107 CM-2 threading dislocations. The complete removal of threading dislocations was accomplished by patterning to 70 gm by 70∼tm square regions followed by thermal annealing for 30 minutes at temperatures greater than 5000C. Neither post-growth annealing alone nor post-growth patterning alone had a significant effect. The effectiveness of this approach dminishes significantly below 500 C so that annealing at 400 C produces no measurable effect. We propose that the underlying mechanism for dislocation removal is the thermally activated glide of dislocations to the sidewalls of patterned regions, as promoted by sidewall image forces.