用于微电容检测的C/V电路设计与研究

结合电荷放大原理,通过设计高性能的运算放大器,较好地完成了杂散电容的屏蔽,实现了高可靠性的微电容检测。采用CSMC0.5μmCMOS工艺,用Cadence Spectre对其进行仿真验证,能精确检测出aF量级的微电容。结合考虑不可避免的工艺误差,对差分标称电容的失配进行分析与校准。结果表明:失配仅带来固定的失调,不会对C/V电路的灵敏度造成显著的影响。     

基于电流镜的微电容式传感器接口电路研究

在集成微电容式传感器的研究中,由于敏感电容值的变化量非常微小,其接口电路的研究对传感器性能提升是至关重要的。设计了一种基于电流镜原理检测的微电容式传感器接口电路,电路由电容转换电压电路、减法器电路、脉冲电路、缓冲器电路等组成。基于0.18μm CMOS工艺库对电路进行设计仿真,结果表明该电路便于与敏感电容兼容,输出电压与敏感电容成线性关系,其检测精确度高、范围广。     

基于充放电原理实现的微电容测量电路

具有抗分布电容以及简单实用等特性的充放电电路是目前微电容测量中广泛采用的一种测量电路。本文对基于充放电原理的微电容测量电路进行了深入研究，并介绍一种基于充放电原理的实用电路。     

微电容式传感器信号检测电路的设计

微电容传感器检测电路是微电容传感器中的关键技术,由于微电容传感器的电容变化量很小,电路中的杂散电容对传感器的影响就会非常大,所以微电容测量电路必须具备大动态范围、高测量灵敏度、低噪声、抗杂散性好等性能。因此提出了电桥式交流电容检测电路。首先将转换后的电压信号加载到高频正弦激励信号中,然后通过放大等一系列处理得到输出电压,最后根据待测电容与输出电压的关系得到待测电容的容抗。(１)采用Multisim仿真软件对提出的电桥式交流电容检测电路进行了调试及可行性验证。(２)在设计的基础上对电路进行了实物焊接和调试。(３)利用信号发生器和示波器对一批已调试的微电容进行了实验验证。实验结果表明,提出的电桥式交流电容检测电路测量的输出电压与理想情况下的输出电压基本一致?且该电路能很好地抑制寄生电容的影响,有良好的线性和稳定性。     

一种可配置的电容-电压转换电路

提出了一种检测微小电容信号的可配置的电容-电压转换电路。该电路由电容补偿电路、电荷积分电路、采样保持电路、低通滤波和缓冲器组成。使用调制解调的电容检测方法,实现了电容-电压转换。仿真结果表明,电容分辨率为1.70aF/√Hz,输出电压信号与电容差成正比,确定系数R²为0.999 99。电路中的积分电容值、放大增益、补偿电容和带宽均可以通过编程灵活设定。该电容-电压转换电路可用于MEMS及其他电容式传感器。     

一种新的不受寄生电容影响的电容式传感器接口电路

给出了一种新的用于微小电容检测的接口电路 .在电荷传送电路的基础上,引入了一个用于参考微变电容读出的电荷传送电路部分,将检测电路与参考电路的输出进行差分放大,从而大大提高了电路的稳定性和检测灵敏度,同时此电路也保持了电荷传送电路检测微小电容变化不受寄生电容影响的特性.     

0．18μm CMOS工艺10Gb／s VCSEL电压驱动器设计

采用SMIC0．18μm1P6M混合信号CMOS工艺设计了10Gb／sVCSEL电压驱动器,可以用于驱动共阴结构的VCSEL。电路采用了RC负反馈技术和C3A（电容耦合电流放大器）结构,仿真结果表明,电路在10Gb／s速率下工作性能良好,最高可工作至12．5Gb／s。电路采用1．8V和3．5V电压供电,直流总功耗为164mw。     

一种新的不受寄生电容影响的电容式传感器接口电路

给出了一种新的用于微小电容检测的接口电路 .在电荷传送电路的基础上,引入了一个用于参考微变电容读出的电荷传送电路部分,将检测电路与参考电路的输出进行差分放大,从而大大提高了电路的稳定性和检测灵敏度,同时此电路也保持了电荷传送电路检测微小电容变化不受寄生电容影响的特性.     

用于电机驱动芯片的高压电荷泵电路设计

基于开关电容系统理论,提出了一种用于步进电机芯片中H桥驱动电路的电荷泵电路。电路设计了零温度系数的高压压差检测电路、线形调制的反馈控制电路和泵电容充电电流控制电路。基于HHNEC 0.35μm BCD工艺平台进行电路设计,并完成流片。测试结果显示,电荷泵电路输出电压跟随输入电压线性变化,输出电压范围为13 V~41 V,纹波电压大小约为560 mV。所获结果与设计目标保持一致,证明了设计思想的正确性。     

采用交流电源供电的低功耗开关电容电路

提出一种新的低功耗开关电容电路设计方法.新的电路结构充分利用开关电容电路的工作特点,同时采用ACP交流电源对电路进行供电.当电路工作在采样相位阶段时,关闭OTA放大器电源以达到降低电路功耗的目的.电路仿真基于CSMC 5V 0.6μm CMOS工艺,与传统的采用DCP直流电源供电的开关电容电路相比,新的ACPSC低功耗开关电容电路可以取得降低40%电路功耗的效果.ACPSC电路技术经过流片测试,验证了电路功能的有效性.     

单一平面电容式漏水检测传感器的研究

针对北方地区冬季暖气管道漏水可能导致的大型设备机房或重要仪器损坏的问题,提出了一种用于管道漏水检测的单一平面电容式传感器的设计方案。该装置利用平面电容原理,检测水滴落在平面电容上时引起的电容变化,采用微电容测量电路将电容转换成频率,然后通过单片机处理后计算出电容值,通过和预先设定的阈值电容的比较来判断平板上是否漏水。经实际试验,该方案实施的平面电容式漏水检测传感器应用于管道漏水检测具有结构简单、成本便宜、性能可靠的特点。     

Linear frequency modulation of voltage-controlled oscillator using delay-line feedback

This letter proposes a structure for a voltage-controlled oscillator (VCO) circuit which operates in a frequency range of 4.0-4.3 GHz and can achieve a highly linear frequency sweep without any additional compensation circuit. The VCO consists of an amplifier and a feedback circuit only. The feedback circuit compensates for the phase delay of a transmission line with a varactor and sets the closed-loop phase change close to 360/spl deg/. The measured maximum deviation from a linear frequency sweep is /spl sim/1.2 MHz when the varactor capacitance C/sub V/ of the VCO is related to the control voltage V/sub C/ by C/sub V//spl prop/V/sub C//sup -1.06/. The spectral distribution of the beat frequency between the VCO output and delayed VCO output shows that the proposed VCO has excellent linearity in frequency modulation.     

加速度传感器信号处理集成电路的研制

设计并制作了一种用于差分电容式加速度传感器的信号处理电路。该电路具有模拟和脉宽调制两种输出方式 ,能够将差分电容的变化通过模拟电平和输出脉冲信号的占空比表征 ,实现了对差分电容式加速度传感器信号的测量。电路中集成了自检测驱动单元。电路采用 4 μmP阱CMOS工艺制作。初步测试结果表明 :在 1～ 5 pF内 ,电路的灵敏度为 10 .7V/ pF ,可满足大多数差分电容式传感器信号处理的要求。     

A low input capacitance voltage follower in a compatible silicon-gate MOS-bipolar technology

Using a compatible silicon-gate p-MOS-bipolar technology (SIGBIP), a voltage follower is described with protected MOSFET input stage featuring less than 1-pA input current, less than 0.1-pF input capacitance, 10-MHz bandwidth, 20-/spl mu/V p-t-p noise from 1 Hz to 100 kHz. Offset drift is less than 30 /spl mu/V//spl deg/C. The circuit is based on a new very high-gain differential stage which allows full bootstrapping of all its input capacitances. The circuit measures only 0.9 mm/SUP 2/ and is mounted in a 4-pin TO-18 package. The circuit can successfully be used for charge measurements, and especially for wide-band measurements from very high impedance sources (>10 M/spl Omega/) as occurring in bioelectronics, biochemistry, etc.     

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)

This paper presents two circuit implementations for the differential capacitance read scheme (DCRS) in ferroelectric random-access memories (FeRAM). Compared to the conventional read scheme, DCRS achieves a faster read access by activating the sense amplifiers immediately after a wordline is activated. By relying on the capacitance difference instead of the charge difference, DCRS avoids raising the highly capacitive platelines until after the read is complete. We have implemented this scheme in a 0.35-/spl mu/m CMOS+Ferro test chip that includes an array of 256 /spl times/ 32 2T-2C cells. The test chip measures an access time of 45 ns at a power supply of 3 V.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

一种应用于DC/DC转换器的自举电路设计

设计了一种适用于DC/DC转换器的自举升压电路.采用该电路可将功率PMOS管替换为NMOS管.在相同尺寸条件下,NMOS管具有较小的导通电阻,从而提高DC/DC转换器的效率.电路基于华宏NEC的0.35 μm BCD工艺,利用Cadence中的Spectre进行了验证.并给出了该自举电路的设计思想、电路的工作原理,以及自举电容最小值的计算.当电源电压降至1.4 V,电路仍能保持正常工作.当自举电容为10 nF,电源电压为5 V,工作频率可高达2 MHz.     

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 /spl mu/m, the inner-sidewall-oxide fringing capacitance (C/sub FIS/), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V/sub G/=0.3 V and V/sub D/=1 V, is the second largest contributor to the gate-source capacitance (C/sub GS/). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 /spl mu/m, C/sub FIS/ cannot be overlooked for modeling gate-source/drain capacitance (C/sub GS//C/sub GD/).