硅／硅键合界面的正电子湮没分析

硅/硅键合是硅功率器件,功率集成电路以及集成传感器衬底制备新技术之一。键合界面的缺陷直接影响器件性能。我们采用正电子湮没技术对N/N~+硅键合片界面缺陷进行了研究。由正电子湮没谱可知:键合引入了界面缺陷,但其缺陷密度小于热扩散形成的N~-/N~+片而引入的缺陷。界面缺陷主要是一些复杂的空位团和微型空洞组成。而且在不同的退火温度下,缺陷状态不同,在高于键合温度下退火。可使键合片具有与原始硅片相近的特性。     

硅—硅键合界面的TEM观察

本文主要利用电子透射显微镜观察硅片直接键合界面,在界面处存在一无定型过渡区,证实了依靠硅片表面吸附的羟基作用完成键合时,在界面会留下极薄的硅氧化物无定形区.     

直接键合硅片界面键合能的理论分析

直接键合硅片界面的键合能依赖于界面成键的密度 ,是退火温度和时间的函数 ,界面反应激活能决定着成键的行为 .硅片键合能随退火温度分两步增加 ,这种现象被归因于界面反应存在两种不同的激活能 .将硅本征氧化层与硅热氧化层两种键合界面在退火过程中的行为进行了理论分析与比较 .硅本征氧化层的键合能随温度的增加要比热氧化层界面的大 .键合能的饱和时间与激活能密切相关     

直接键合硅片界面键合能的理论分析

直接键合硅片界面的键合能依赖于界面成键的密度,是退火温度和时间的函数,界面反应激活能决定着成键的行为．硅片键合能随退火温度分两步增加,这种现象被归因于界面反应存在两种不同的激活能．将硅本征氧化层与硅热氧化层两种键合界面在退火过程中的行为进行了理论分析与比较．硅本征氧化层的键合能随温度的增加要比热氧化层界面的大．键合能的饱和时间与激活能密切相关．     

硅-硅键合晶片在减薄过程中产生的应力及影响

硅-硅键合晶片在机械减薄过程中产生的应力使硅片产生弯曲变形,这种变形在其后的加工过程中会使图形发生扭曲或位移,导致硅片加工中途报废.经过应力消除处理后可以顺利完成加工.     

硅-硅键合界面氧化层模型与杂质分布的模拟

硅-硅直接键合的硅片界面存在一层很薄的氧化层,其化学成分是非化学计量比的氧化物S iOw(0相似文献   

用于制备SOI材料的基于硅片键合和双层多孔硅剥离的薄外延硅膜转移技术

采用在阳极化反应时改变电流强度的办法 ,在高掺杂的 P型硅 (111)衬底上制备了具有不同多孔度的双层结构多孔硅层 .用超高真空电子束蒸发技术在多孔硅表面外延生长了一层高质量的单晶硅膜 .在室温下 ,该外延硅片同另一生长有热二氧化硅的硅片键合在一起 ,在随后的热处理过程中 ,键合对可在多孔硅处裂开 ,从而使外延的单晶硅膜转移到具有二氧化硅的衬底上以形成 SOI结构 .扫描电镜、剖面投射电镜、扩展电阻和霍尔测试表明 SOI样品具有较好的结构和电学性能     

用于制备SOI材料的基于硅片键合和双层多孔硅剥离的薄外延硅膜转移技术

采用在阳极化反应时改变电流强度的办法,在高掺杂的P型硅(111)衬底上制备了具有不同多孔度的双层结构多孔硅层.用超高真空电子束蒸发技术在多孔硅表面外延生长了一层高质量的单晶硅膜.在室温下,该外延硅片同另一生长有热二氧化硅的硅片键合在一起,在随后的热处理过程中,键合对可在多孔硅处裂开,从而使外延的单晶硅膜转移到具有二氧化硅的衬底上以形成SOI结构.扫描电镜、剖面投射电镜、扩展电阻和霍尔测试表明SOI样品具有较好的结构和电学性能.     

用于制造传感器、执行器和微结构的硅直接键合(SDB)工艺

硅片直接键合(SDB),即硅—硅键合,是一种把两个硅片直接键合在一起的一种工艺,它不需使用如聚合物或熔融玻璃的中间粘结剂,也不需用如在玻璃一硅阳极键合中的外加电场.这种工艺已经在微电路研制中用来制造SOI衬底同样在制造硅传感器、执行器和微结构方面得到广泛应用.     

硅-硅直接键合后硅片的机械减薄过程北大核心

硅-硅直接键合硅片的机械减薄工艺对器件的性能有很大的影响。采用磨削、化学腐蚀和机械/化学抛光的方法对硅-硅直接键合硅片进行减薄加工,分析了减薄过程中各个工序键合片的平整度、弯曲度和翘曲度变化,并对减薄后硅片的厚度均匀性进行了考察。本次实验最终获得了几何参数良好、厚度满足要求且均匀的晶片。磨削过程会使弯曲度和翘曲度升高,可以通过化学腐蚀的方法降低弯曲度和翘曲度,化学腐蚀过程虽然使平整度升高,但可以通过机械/化学抛光的方法降低平整度。采用该减薄技术对直接键合硅片进行机械减薄具有可行性。     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

Selective bonding and encapsulation for wafer-level vacuum packaging of MEMS and related micro systems

A laser-assisted bonding technique is demonstrated for low temperature region selective processing. A continuous wave carbon dioxide (CO₂) laser (λ=10.6 μm) is used for solder (Pb37/Sn63) bonding of metallized silicon substrates (chips or wafers) for MEMS applications. Laser-assisted selective heating of silicon led to the reflow of an electroplated, or screen-printed, intermediate solder layer which produced silicon–solder–silicon joints. The bonding process was performed on fixtures in a vacuum chamber at an air pressure of 10⁻³ Torr to achieve fluxless soldering and vacuum encapsulation. The bonding temperature at the sealing ring was controlled to be close to the reflow temperature of the solder. Pull test results showed that the joint was sufficiently strong. Helium leak testing showed that the leak rate of the package met the requirements of MIL-STD-883E under optimized bonding conditions and bonded packages survived thermal shock testing. The testing, based on a design of experiments method, indicated that both laser incident power and scribe velocity significantly influenced bonding results. This novel method is especially suitable for encapsulation and vacuum packaging of chips or wafers containing MEMS and other micro devices with low temperature budgets, where managing stress distribution is important. Further, released and encapsulated devices on the sealed wafers can be diced without damaging the MEMS devices at wafer level.     

Effect of nanotopography in direct wafer bonding: modeling and measurements

Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.     

无压力辅助硅/玻璃激光局部键合

提出了一种新的无需外压力作用的硅/玻璃激光局部键合方法,通过对晶圆进行表面活化处理,选择合适的激光参数及加工环境,成功地实现了无压力辅助硅/玻璃激光键合.同时研究了该键合工艺参数如激光功率、激光扫描速度、底板材料等的影响.实验表明,激光功率越大,扫描速度越小,键合线的宽度就越大.实验结果显示,该方法能有效减少键合片的残余应力,控制键合线宽,并能得到较好的键合强度.该工艺可为MEMS器件的封装与制造提供简洁、快速、键合区可选择的新型键合方法.     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

Si/Si键合界面的超声显微成像(英文)

硅/硅键合片在MEMS器件的生产中得到了应用。如果硅片的表面被微观粒子或被污染液体中的残余物所沾污,硅/硅键合界面就会产生空洞。如果这些空洞没有被及时发现,将给后道工序带来严重的问题,并降低成品率。超声显微成像对于不同材料的界面反应非常敏感,对硅/硅界面存在的空洞很容易声学成像。使用超声显微成像能够检测到键合界面存在的空洞,因而可以把有缺陷的硅片在造成进一步的损失之前清除掉。高分辨率的超声显微成像可以辨别出直径5μm的空洞。     

Aligned wafer bonding: A key to three dimensional microstructures

Successful fabrication of critically aligned three dimensional structures has been achieved by combining precision alignment procedures and techniques for direct silicon bonding. This produces three dimensional bonded layers that might include combinations of mechanical, electronic and/or optical elements formed in separate prefabricated layers. We call this techniquealigned wafer bonding. The precise aligned bonding of the features was done with an Optical AssociatesHyperline 400 Infrared Aligner. This machine can hold two imprinted wafers face to face while projecting an infrared image of the surfaces to a viewing screen. An array of alignment marks were etched into the surface of silicon wafers with hot potassium hydroxide. These V-grooves were then precisely aligned and the wafers were brought into contact for initial bonding. Subsequent high temperature annealing was used to strengthen and complete the chemical bonding. The instrumentation used in this work required alignment features with a vertical dimension of 30 micrometers to produce a suitable infrared image. We found that the apparent size of the images produced by the optical system limited the accuracy in precision alignment. However, with reduced wafer separation, we achieved wafer alignment with an accuracy of better than 5 micrometers. This technique would generally be used for the precision alignment and bonding of complementary micromechanical, electrical, or optical structures during the formation of three dimensional devices. The details of the aligned wafer bonding and its applications are presented.     

Transient effects in rapid thermal processing

Using a realistic model of a rapid thermal processing chamber including Navier-Stokes calculations of the gas losses, the stresses and yield strengths of silicon wafers were determined for several linear ramp rates. It was found that the stress to yield strength ratio is a sensitive function of the ramp rate and the radiant uniformity. Radiation patterns that produce good steady-state thermal nonuniformity overheat the wafer edges during heating transients, leading to high stress levels     

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.     

Fabrication and Characterization of 150-mm Silicon-on-Polycrystalline Silicon Carbide Substrates

Silicon-on-insulator (SOI) substrates can reduce radiofrequency (RF) substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps heat generated by devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of polycrystalline silicon and polycrystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable BOX and the silicon substrate. Substrates of 150 mm were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low-resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared with each other. Results showed that the Si-on-poly-SiC wafer had 2.5 times lower thermal resistance and exhibited equal or better electrical performance compared with the SOI reference wafer.