基于级间电容抵消技术的74~88 GHz高性能CMOS LNA设计北大核心

采用55 nm CMOS工艺,面向毫米波雷达应用,设计了一款74~88 GHz高性能CMOS低噪声放大器(LNA)。该LNA应用共源共栅结构,为了改善噪声系数、提高稳定性增益,采用级间寄生电容抵消的电感反馈共栅短接技术和基于反相双圈耦合的等效跨导增强技术。和传统共栅短接技术相比,级间寄生电容抵消的电感反馈共栅短接技术改善噪声系数1.58 dB,提高稳定性增益7.67 dB。芯片测试结果表明,LNA峰值增益为17.1 dB,最小噪声系数为6.3 dB,3 dB带宽为14 GHz(74.8~88.8 GHz),在78 GHz中心频率处输入1 dB压缩点(IP1dB)为-10.2 dBm,功耗为102 mW。     

CMOS毫米波低功耗超宽带共栅低噪声放大器

陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA).该LNA用标准90-nm RFCMOS工艺实现并具有如下特征:在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2dB,平均NF在27 ～ 42 GHz频段内为5.1 dB;S11在整个测试频段内小于-11 dB.40 GHz处输入三阶交调点(IIP3)的测试值为+2 dBm.整个电路的直流功耗为5.3 mW.包括焊盘在内的芯片面积为0.58 mm×0.48 mm.     

一种2.2~4 GHz高增益低噪声放大器

采用0.25 μm GaAs赝配高电子迁移率晶体管(pHEMT)工艺,设计并实现了一种应用于5G通信2.2~4 GHz频段的高增益共源共栅低噪声放大器(LNA)。通过将并联RC负反馈与共栅接地电容结合,不使用源极电感,实现了宽带高增益的LNA设计。测试结果表明,2.2~4 GHz频段增益大于24 dB,输出3阶互调(OIP3)为28 dBm,噪声系数(NF)小于0.78 dB,功耗为190 mW,芯片面积为(810×710) μm²。综合指标(FOM)为14.4 dB,与同类LNA相比具有一定的优势。     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

2～18 GHz GaAs超宽带低噪声放大器MMIC

基于90 nm GaAs赝配高电子迁移率晶体管(PHEMT)工艺设计并制备了一款2～18 GHz的超宽带低噪声放大器(LNA)单片微波集成电路(MMIC)。该款放大器具有两级共源共栅级联结构，通过负反馈实现了超宽带内的增益平坦设计。在共栅晶体管的栅极增加接地电容，提高了放大器的高频输出阻抗，进而拓宽了带宽，提高了高频增益，并降低了噪声。在片测试结果表明，在5 V单电源电压下，在2～18 GHz内该低噪声放大器小信号增益约为26.5 dB,增益平坦度小于±1 dB,1 dB压缩点输出功率大于13.5 dBm,噪声系数小于1.5 dB,输入、输出回波损耗均小于-10 dB,工作电流为100 mA,芯片面积为2 mm×1 mm。该超宽带低噪声放大器可应用于雷达接收机系统中，有利于接收机带宽、噪声系数和体积等的优化。     

基于噪声抵消技术的超宽带低噪声放大器

实现了一款超宽带低噪声放大器( UWB LNA)。该UWB LNA由输入级、中间级和输出级组成。在输入级,采用两个共栅配置构成了噪声抵消技术,减少了噪声,在此结构基础上进一步采用了跨导增强技术,提高了增益。同时插入的电感Lin提高了LNA在宽带范围内的增益平坦度。中间级放大器,在漏极并联电感产生零点,提高了LNA的带宽。输出级为源极跟随器,较好实现了LNA的阻抗匹配。基于0.18μm TSMC CMOS工艺仿真验证表明,在4 GHz~10 GHz频带范围内,电压增益( S21)为(19.2±0.3)dB,噪声系数(NF)介于2.1 dB~2.4 dB之间,输入、输出反射系数(S11、S22)均小于-10 dB。在9 GHz时,输入三阶交调点(IIP3)达到-7 dBm。在1.8 V的电源电压下,功耗为28.6 mW。     

低压中和化CMOS差分低噪声放大器设计

以设计低电压LNA电路为目的,提出了一种采用关态MOSFET中和共源放大器输入级栅漏寄生电容Cgd的CMOS差分低噪声放大器结构.基于该技术,采用0.35μmCMOS工艺设计了一种工作在5.8GHz的低噪声放大器.结果表明,在考虑了各种寄生效应的情况下,该低噪声放大器可以在0.75V的电源电压下工作,其功耗仅为2.45mW.在5.8GHz工作频率下:该放大器的噪声系数为2.9dB,正向增益S21为5.8dB,反向隔离度S12为-30dB,S11为-13.5dB.     

宽带高增益输出平衡CMOS低噪声放大器的设计

设计了一种带片内变压器、适用于0.05～2.5 GHz频段的宽带低噪声放大器(LNA).电路设计采用了并行的共栅共源放大结构,将从天线接收到的单端输入信号转换为一对差分信号输出给后级链路.针对变压器结构的LNA噪声系数不够低和输出不平衡的问题,采用了缩放技术、噪声消除技术以及两级的全差分放大器作为输出缓冲级,来有效降低电路的噪声系数,提高增益和输出平衡度.电路采用TSMC 0.18μm 1P6M RF CMOS工艺设计仿真和流片,测试结果表明:在0.05 ～ 2.5 GHz频带范围内,该LNA的最高功率增益达24.5 dB,全频段内噪声系数为2.6～4 dB,输入反射系数小于-10 dB,输出差分信号幅度和相位差分别低于0.6dB和1.8°.     

1GHz 0.5μm CMOS低噪声放大器的设计

从低噪声放大器(LNA)的设计原理出发,提出并设计了一种工作于1GHz的实用LNA.电路采用共源-共栅的单端结构,用HSPICE软件对电路进行分析和优化.模拟过程中选用的器件采用TSMC 0.5μm CMOS工艺实现.模拟结果表明所设计的LNA功耗小于15mW,增益大于10dB,噪声系数为1.87dB,IIP3大于10dBm,输入反射小于-50dB.可用于1GHz频段无线接收机的前端.     

1V高线性度2.4GHz CMOS低噪声放大器

讨论了低噪声放大器(LNA)在低电压、低功耗条件下的噪声优化及线性度提高技术.使用Chartered 0.25μm RF CMOS 工艺设计一个低电压折叠式共源共栅LNA.后仿真结果表明在1V电源下,2.36GHz处的噪声系数NF仅有1.32dB,正向增益S21为14.27dB,反射参数S11、S12、S22分别为 -20.65dB、-30.27dB、-24dB,1dB压缩点为-13.0dBm,三阶交调点IIP3为-0.06dBm,消耗的电流为8.19mA.     

S-band low noise amplifier using 1 μm InGaAs/InAlAs/InP pHEMT

This paper discusses the design of a wideband low noise amplifier (LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications. The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT. Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz. A common-drain in cascade with a common source inductive degeneration, broadband LNA topology is proposed for wideband applications. The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss (S₁₁ < -10 dB, S₂₂ < -11 dB). This LNA exhibits an input 1-dB compression point of -18 dBm, a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

A low-power,low-noise and high linearity 60 GHz wideband CMOS low-noise amplifier for wireless personal area network (WPAN) systems

A low power and low noise figure (NF) 60 GHz wideband low-noise amplifier (LNA) with excellent phase linearity for wireless personal local network (WPAN) systems using standard 90 nm CMOS technology is reported. To achieve sufficient power gain (S₂₁) and reverse isolation (S₁₂), the LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S₁₁ better than ?10 dB for frequencies 55.1–59.5 GHz, S₂₂ better than ?10 dB for frequencies 55.1–59.4 GHz, S₁₂ better than ?42.6 dB for frequencies 50–64 GHz, and group delay variation smaller than ±13.25 ps for frequencies 50.4–63 GHz. Additionally, high and flat S₂₁ of 9.9 ± 1.5 dB is achieved for frequencies 50.4–62.9 GHz, which means the corresponding 3-dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves minimum NF of 3.88 dB at 55.5 GHz and NF of 4.73 ± 0.85 dB for frequencies 50–63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.