A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while oper...     

无源温度标签中的超低功耗CMOS温度传感器设计

设计了一种适用于无源超高频(UHF)温度标签的超低功耗CMOS温度传感器电路.该电路利用衬底pnp晶体管产生随温度变化的电压信号,同时采用了逐次逼近寄存器(SAR)转换和∑-△调制相结合的模拟数字转换方式.为了降低电源电压波动以及采样电容电荷泄漏对传感器测温精度的不利影响,提出了一种具有漏电保护机制的采样电路.基于0.18 μm CMOS工艺设计实现了该传感器的电路和版图,其中版图面积为550 μm×450 μm,并利用Cadence Spectre仿真工具对电路进行了仿真.仿真结果表明,在-40～ 125℃,传感器的系统误差为-1.4～2.0℃,测温分辨率达到0.02℃;在1.2～2.6 V电源电压内,传感器输出温度波动小于0.3℃;在1.2V电源电压下传感器电路(不合控制逻辑及数字滤波器)的功耗仅为2.4μW.     

一种全nMOS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管. 存取管的沟道长度小于下拉管的沟道长度. 由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑“1" . 存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的“读”操作. 背栅反馈同时增强了SRAM单元的静态噪声容限(SNM). 该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积. 对SRAM单元的读写速度和功耗做了仿真和讨论. 该SRAM单元可以工作在0.5V电源电压下.     

CMOS超高频整流器

提出了一个适用于无源UHF RFID标签芯片的全CMOS整流器.整流器包括射频-直流转换电路、偏置电路、直流-直流转换电路和振荡器电路.整流器的工作频率范围是860～960 MHz.基于0.18μm,1p6m的标准数字CMOS工艺,设计并实现了无源UHF RFID标签芯片的整流器.该设计采用开关电容电路技术动态地消除了CMOS管开启电压的问题,在标准数字CMOS工艺下实现了高效率的超高频整流器.整流器的面积为180μm×140μm.当输入900MHz,-16dBm的射频信号时,整流器的输出电压为1.2V,启动时间为980μs.     

（英）CCNet:面向多光谱图像的高速船只检测级联卷积神经网络

针对实现遥感图像中船只目标的快速检测,提出了一个采用多光谱图像、基于级联的卷积神经网络(CNN)船只检测方法CCNet。该方法所采用两级级联的CNN依次实现感兴趣区域(ROI)的快速搜索、基于感兴趣区域的船只目标定位和分割。同时,采用含有更多细节信息的多光谱图像作为CCNet的输入,能够提升网络提取特征鲁棒性,从而使得检测更加精确。基于SPOT 6卫星多光谱图像的实验表明：与当前主流的深度学习船只检测方法相比,该方法能够在实现高检测精准度的基础上将检测速度提高5倍以上。     

一种基于40 nm CMOS工艺的40 Gbit/s低噪声跨阻放大器

采用40 nm CMOS工艺,设计了一个工作在40 Gbit/s数据速率的高速低噪声跨阻放大器(TIA)。为了同时兼顾噪声和带宽性能,创造性提出了一种多级串联跨阻放大器结构。输入级采用基于反相器结构的伪差分跨阻放大器,通过增加反馈电阻来减小输入电流噪声,第二级的前向运放用来抑制后级均衡器的噪声,第三级用连续时间线性均衡器(CTLE)对前级不足的带宽进行补偿,后面的三级限幅放大器(LA)对电压信号进一步放大。限幅放大器利用并联电感峰化技术和负跨导技术来提高带宽和增益。最终,信号由输出驱动器(OD)输出到片外,输出驱动器采用T-COIL技术。仿真结果表明,整条链路可以实现84 dBΩ和63 dBΩ的跨阻增益,带宽分别为31 GHz和34 GHz,输入电流积分噪声(rms)为1.75 μA。     

一种基于ZigBee应用的低功耗2.4GHz无线收发机

This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier(LNA) with a noise cancellation function,a new inverter-based variable gain complex filter (VGCF) for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier(PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier(PA) to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves—95 dBm of sensitivity,28 dBc of image rejection,and -8 dBm of third-order input intercept point(IIP3).The transmitter can deliver a maximum of+3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm~2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.     

一种新颖的低噪声放大器的噪声优化方法

This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.     

一种全nMoS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管.存取管的沟道长度小于下拉管的沟道长度.由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑"1".存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的"读"操作.背栅反馈同时增强了SRAM单元的静态噪声容限(SNM).该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积.对SRAM单元的读写速度和功耗做了仿真和讨论.该SRAM单元可以工作在0.5V电源电压下.     

一种面积紧凑的视觉芯片处理单元存储器

This paper presents a novel compact memory in the processing element （PE） for single-instruction multiple-data （SIMD） vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.