基于延时锁定环的时间数字转换器设计

A time-to-digital converter(TDC) based on a reset-free and anti-harmonic delay-locked loop(DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid "false locking". Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18 m CMOS technology, and its core area occupies 0.7 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.     

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.     

一种适用于相变存储器的低抖动锁相环时钟

A fully integrated low-jitter,precise frequency CMOS phase-locked loop(PLL) clock for the phase change memory(PCM) drive circuit is presented.The design consists of a dynamic dual-reset phase frequency detector(PFD) with high frequency acquisition,a novel low jitter charge pump,a CMOS ring oscillator based voltage-controlled oscillator(VCO),a 2nd order passive loop filter,and a digital frequency divider.The design is fabricated in 0.35μm CMOS technology and consumes 20 mW from a supply voltage of 5 V.In terms of the PCM’s program operation requirement,the output frequency range is from 1 to 140 MHz.For the 140 MHz output frequency,the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.     

Design of a 10 bit high resolution,high speed time-to-digital converter using a two-step pulse-train time amplifier

Ahigh resolution and fast conversion rate time-to-digital converter (TDC) design based on time amplifier (TA) is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0.8 ps and a conversion rate of 150 MS/s are achieved while consuming 2.1 mW power consumption.     

A 750 MHz semi-digital clock and data recovery circuit with 10~(-12) BER

A semi-digital clock and data recovery（CDR） is presented.In order to lower CDR trace jitter and decrease loop latency,an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13μm standard 1P8M CMOS process,our CDR is integrated into a high speed serial and de-serial（SERDES） chip.Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency,while the bit error rate of the recovery data is less than 10×10^-12.     

A Fractional-N CMOS DPLL with Self-Calibration

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented.The self-calibration technique is employed to acquire wide lock range,low jitter,and fast acquisition.The DPLL works from 60 to 600MHz at a supply voltage of 1.8V.It also features a fractional-N synthesizer with digital 2nd-order sigma-delta noise shaping,which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum.The DPLL has been implemented in SMIC 0.18μm 1.8V 1P6M CMOS technology.The peak-to-peak jitter is less than 0.8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.     

2.5 Gb/s 16∶1 MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is (1.8) mm~(2).     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

一种误码率为10-12的750MHz半数字结构时钟和数据恢复电路的研究

A semi-digital clock and data recovery (CDR) is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1P8M CMOS process, our CDR is integrated into a high speed serial and de-serial (SERDES) chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.     

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.     

GM-APD阵列高精度像素读出电路设计

提出并设计了一种适用于激光3D成像的盖革模式雪崩光电二极管（Geiger-mode avalanche photodiode,GM-APD）阵列像素读出电路。基于飞行时间（time-of-flight,TOF）原理,像素读出电路主要由两部分组成:有源淬火电路（active quenching circuit,AQC）和时间数字转换器（time-to-digital converter,TDC）。所采用的TDC是粗细结合的两段式计数方式,成功实现了时钟频率和时间分辨率间的折中。基于内插技术,由粗计数的线性反馈移位寄存器和细计数的延时线型TDC共同实现了高达18-bit的动态范围。同时两者的时钟频率分别降低至250 MHz和500 MHz,分别是常规设计频率的1/20和1/10,大大降低了设计和应用难度。电路采用SMIC 0.18 m工艺设计,后仿结果显示达到了200 ps的高精度时间分辨率,对应的距离分辨率为3 cm,完全能够满足3 km激光3D成像中的测距要求。像素电路版图面积小于5095 m2,总功耗为0.89 mW,具有小面积和低功耗的优势。     

一种新颖的低非线性全数字多相时钟产生电路

通过对传统的全数字多相位时钟产生电路进行分析和总结,提出一种新颖的延时校准算法。该算法通过优化调整延时单元的顺序,大大改善了全数字多相位时钟产生电路的非线性。整个电路基于全数字延迟锁相环,采用0.13μm CMOS工艺实现,并成功用于时间数字转换器中。输入时钟频率范围在110 MHz到140 MH间,对应的输出相位差为446 ps到568 ps,积分非线性小于0.35 LSB,微分非线性小于0.33 LSB。     

An all digital PLL with an active inductor DCO for LTE applications in 0.13 μm CMOS

In this paper, we propose a low-power all digital phase-locked loop with a wide input range, and a high resolution TDC that uses phase-interpolator and a time amplifier. The resolution of the proposed TDC is improved by using a phase-interpolator which divides the inverter delay time and the time amplifier which extends the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is improved by using a fine resolution DCO with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range and to operate at a low-power, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally in order to compensate for gain variations. The die area of the ADPLL is 0.8 mm² using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is −120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

An integrated time-to-digital converter with 30-ps single-shotprecision

A time-to-digital converter (TDC) with 32-ps resolution and 2.5-μs measurement range has been integrated in a 0.8-μm BiCMOS process. The TDC is based on a counter with a 100-MHz clock. Two separate time digitizers improve the time resolution by interpolating within the clock period. These interpolators are based on analog dual-slope conversion. According to test results, the single-shot precision of the TDC is better than 30 ps (σ-value) and the nonlinearity is less than ±5 ps when input time intervals range from 10 ns to 2.5 μs. The conversion time is ⩽6.3 μs. Temperature drift, excluding the temperature dependence of the oscillator, is below ±40 ps in the temperature range of -40 to 60°C. The size of this chip, including pads, is 3.5×3.4 mm² and its power consumption is 350 mW     

一种用于TDC的低功耗多相时钟生成电路北大核心

在无人机3D地形测绘中，作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量，文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器，通过优化交叉耦合结构，在保证低功耗的前提下，提升了信号边缘的斜率，增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中，通过对环路带宽的考量选取了极低的偏置电流，在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明，在400 MHz的输出频率下，环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度，相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。     

一种应用于TDC的低抖动延迟锁相环电路设计

本文采用双延迟线和防错锁控制结构,结合对电荷泵等关键模块版图对称性的匹配控制,设计了一种针对（Time-to-Digital Converter,TDC）应用的宽动态锁定范围、低静态相位误差延迟锁相环（Delay-Locked Loop,DLL）电路.基于TSMC 0.35μm CMOS工艺,完成了电路的仿真和流片验证.测试结果表明,DLL频率锁定范围为40MHz-200MHz;静态相位误差161ps@125MHz;在无噪声输入的理想时钟驱动下,200MHz频率点下的峰-峰值抖动最大为85.3ps,均方根抖动最大为9.44ps,可满足亚纳秒级时间分辨的TDC应用需求.     

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm². The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.     

一种基于GRO TDC的高精度片上电源噪声监测方法

介绍了一种以数字模块为主的高精度片上电源噪声监测方法。该方法使用基于门控环形振荡器(GRO)的时间数字转换器(TDC),并有效地利用GRO每一级的信息,可得到比只利用GRO一级作为输出的方法高29倍的精度。基于65nm CMOS工艺,实现了该电源噪声监测器电路,有源区面积为0.014mm2,在1V电源电压下功耗为1.05mW。     

一种用于高速流水线ADC的时钟管理器

文章设计了一种用于高速流水线ADC的时钟管理器,该电路以延迟锁相环(DLL)电路为核心,由偏置电路、时钟输入电路、50%占空比稳定电路和无交叠时钟电路构成。该电路用0.35μmBiCMOS工艺条件下cadence spectre仿真。由测量结果可知,时钟管理器可以实现70MHz~300MHz有效输出。在250MHz典型频率下测得峰值抖动为16ps,占空比为50%,功耗为47mW。仿真结果表明该时钟管理器具有高速度、高精度、低功耗的特点,适用于高速流水线ADC。