用固相外延方法制备Si1-x-yGexCy三元材料

分析了Si1-x-yGexCy三元系材料外延生长的特点,指出原子性质上的巨大差异使Si1-x-yGexCy材料的制备比较困难.固相外延生长是制备Si1-x-y的有效方法,但必须对制备过程各环节的条件进行优化选择.通过实验系统地研究了离子注入过程中温度条件的控制对外延层质量的影响以及外延退火条件的选择与外延层结晶质量的关系.指出在液氮温度下进行离子注入能够提高晶体质量,而注入过程中靶温过高会导致动态退火效应,影响以后的再结晶过程.采用两步退火方法有利于消除注入引入的点缺陷,而二次外延退火存在着一个最佳退火温区.在此基础上优化得出了固相外延方法制备Si1-x-yGexCy/Si材料的最佳条件.     

碳对Si_(1-x-y)Ge_xC_y合金氧化的影响

利用椭圆偏振仪 (EL)、傅里叶红外光谱 (FTIR)研究了 Si1 - x- y Gex Cy 合金分别在 90 0℃和 10 0 0℃干氧气氛下形成氧化物的生长动力学 .结果表明 :在 90 0℃氧化时 ,随着合金中的替代碳含量的增加 ,氧化速率逐渐下降 ;而在 10 0 0℃下氧化超过 10 min后 ,Si1 - x- y Gex Cy 合金的氧化基本上与碳的含量无关 ,与 Si1 - x Gex 的行为一致 .这主要是由于在 10 0 0℃比较长时间的氧化过程中 ,替代位的碳逐渐析出形成 β- Si C沉淀 ,失去了对氧化过程的影响作用 .研究表明对于 Si1 - x- y Gex Cy 薄膜和器件的应用来说 ,氧化的温度必须要小于 10 0 0℃ .     

Si_(1-x-y)Ge_xC_y三元系材料的应变补偿特性

研究了 Si1 - x- y Gex Cy 三元系材料的应变补偿特性 ,分析了固相外延方法制备的样品中注入离子的分布对应变补偿效果的影响 ,指出由于 Ge和 C的投影射程及标准偏差不同 ,二者在各处的组分比并不恒定 ,存在着纵向分布 ,因此各处的应变补偿情况也不尽相同 .利用高斯公式对不同位置的应变补偿效果进行了分析 ,得出了外延层中存在应变完全补偿区域时 Ge、C的峰值浓度比 NGe/ NC应满足一定的取值范围 .通过制备不同 C组分的样品对上述结论进行了验证 ,得出的结果与理论预言基本相符     

Si1-x Gex:C缓冲层的生长温度对Ge薄膜外延生长的影响

用化学气相淀积方法,在Si(100)衬底上生长Si1-x Gex:C合金作为缓冲层、继而外延生长了Ge晶体薄膜,用X射线衍射(XRD)、俄歇电子能谱(AES)、拉曼(Raman)衍射光谱等对所得到的样品进行了表征测量,着重研究了Si1-x Gex:C缓冲层生长温度对样品结构特征的影响.结果表明:Si1-x Gex:C缓冲层中的Ge原子浓度沿表面至衬底方向逐渐降低,其平均组分随着生长温度的升高而降低.这与较高生长温度(760～820℃)所导致的原子扩散效应相关;在Si1-x Gex:C缓冲层上外延生长的Ge薄膜具有单一的晶体取向,薄膜的晶体质量随着温度的升高而降低.     

C离子注入Si中Si-C合金的形成及其特征

利用离子注入和高温退火的方法在 Si中生长了 C含量为 0 .6 %— 1.0 %的 Si1 - x Cx 合金 ,研究了注入过程中产生的损伤缺陷、注入 C离子的剂量及退火工艺对合金形成的影响 ,探讨了合金的形成机理及合金产生的应变分布的起因 .如果注入的 C离子剂量小于引起 Si非晶化的剂量 ,退火过程中注入产生的损伤缺陷容易与 C原子结合形成缺陷团簇 ,难于形成 Si1 - x Cx 合金 ,而预先利用 Si离子注入引进损伤有利于 Si1 - x Cx 合金的形成 ;但如果注入的C离子可以引起 Si的非晶化 ,预先注入产生的损伤缺陷不利于 Si1 - x Cx 合金的形成 .与慢速退火工艺相比 ,快速     

GeSi/Si多层异质外延载流子浓度的分布

通过实验确定了一种与 Gex Si1 - x合金表面具有良好电化学界面的电解液 ,利用电化学 C- V方法研究了多层Gex Si1 - x/ Si异质外延材料的载流子浓度纵向分布 .实验结果表明 :采用这种电解液 ,利用电化学 C- V载流子浓度纵向分布测量仪检测 Gex Si1 - x/ Si异质材料的载流子浓度纵向分布 ,重复性好 ,可靠性高     

用于Si1-xGex异质结外延材料生长的高真空化学汽相外延炉

研制出满足 Si1 - x Gex 异质结薄膜材料生长工艺的高真空化学汽相外延炉 ,详述了该汽相外延设备的性能、结构组成和设计原理 ,并且给出了利用该设备生长 Si1 - x Gex 异质薄膜的实验结果。     

离子注入及退火对GaAs/Si晶体完整性影响的研究

本文用4.2MeV ~7Li离子卢瑟福背散射沟道技术研究了Si上外延GaAs膜在MeV Si离子注入及红外瞬态退火后的再生长过程。实验表明,离子注入可使GaAs外延膜内形成一无序网络,当注入剂量低于某一阈值时,850℃,15秒退火后,损伤区可完全再结晶,再结晶后的GaAs层的晶体质量特别在界面区有很大的改善;当剂量超过该阈值时,出现部分再结晶。激光Raman实验也表明,经过处理后的GaAs层Raman谱TO/LO声子的比率比原生长的样品有很大的降低。     

硅、锗和氩离子注入富硅二氧化硅的电致发光

将Si、Ge和Ar三种离子注入到磁控溅射制备的富硅二氧化硅和热生长的二氧化硅中,在N2气氛中,作550、650、750、850、950和1050℃退火后,进行电致发光研究.对比样品为退火条件相同的未经注入的上述两种二氧化硅.对于离子注入情况,只观察到Au/1050℃退火的离子注入的富硅二氧化硅/p-Si的电致发光.低于1050℃退火的离子注入富硅二氧化硅和上述各种温度下退火的热生长二氧化硅,无论离子注入与否,都未观察到电致发光.Au/未注入富硅二氧化硅/p-Si的电致发光光谱在1.8eV处出现主峰,在2.4eV处还有一肩峰.在Au/Si注入富硅二氧化硅/p-Si的电致发光谱中,上述两峰的     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备Si Ge p MOSFET中引入了低温Si技术.通过在Si缓冲层和Si Ge层之间加入低温Si层,提高了Si Ge层的弛豫度.当Ge主分为2 0 %时,利用低温Si技术生长的弛豫Si1 - x Gex 层的厚度由UHVCVD制备所需的数微米降至4 0 0 nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.0 2 nm.器件测试表明,与相同制备过程的体硅p MOSFET相比,空穴迁移率最大提高了2 5 % .     

Maximum Active Concentration of Ion-Implanted Phosphorus During Solid-Phase Epitaxial Recrystallization

In this paper, we showed that the maximum active P concentration of approximately 2 times10²⁰ cm^-3 exists during solid-phase epitaxial recrystallization (SPER). This maximum active concentration is close to the reported values for other active impurity concentrations during SPER. We introduced the concept of an isolated impurity that has no neighbor impurities with a certain lattice range. Assuming that impurities interact with three or four neighbor impurities, we can explain the activation phenomenon during SPER. According to our model, the isolated P concentration N _iso has a maximum value of approximately 2 times10²⁰ cm^-3 at a total impurity concentration of approximately 10²¹ cm^-3, and it decreases with a further increase in total impurity concentration. Deactivation occurs after the completion of SPER with increasing annealing time, and the active impurity concentration decreases with time but is always higher than the maximum diffusion concentration N _{Diff max}. We also observed that N _{Diff max} is independent of the annealing time despite nonthermal activation in the high-concentration region. We evaluated the dependence of N _{Diff max} on annealing temperatures. We think that this N _{Diff max} can be regarded as the electrical solid solubility N _Esol that the active impurity concentration reaches in thermal equilibrium. We observed the transient enhanced diffusion (TED) after the completion of SPER, and that, the deactivation process continues during and after TED, and the corresponding diffusion coefficient is still much higher than that in thermal equilibrium even after TED has finished, which suggests that the deactivation process releases point defects.     

Special features of electrical activation of 28Si in single-crystal and epitaxial GaAs subjected to rapid thermal annealing

Concentration profiles of ²⁸Si implanted in single-crystal and epitaxial GaAs were determined by measuring the C-V characteristics after the postimplantation rapid thermal annealings for 12 s at T=825, 870, and 905°C. The temperature dependence of Hall mobility of electrons in the Si-implanted layers subjected to the same annealings was determined by the Van der Pauw method within the range of 70–400 K. As distinct from conventional thermal annealing (for 30 min at 800°C), the rapid thermal annealing brings about a diffusive redistribution of silicon to deeper layers of GaAs for the materials of both types, with the diffusivity of silicon being twice as high in single-crystal GaAs as that in GaAs epitaxial layers. Analysis of temperature dependence of electron mobility in ion-implanted layers following a rapid thermal annealing indicates a significantly lower concentration of the defects limiting the mobility as compared to the case of a conventional thermal annealing for 30 min.     

A high-temperature radiation-resistant rectifier based on p<Superscript>+</Superscript>-n junctions in 4H-SiC ion-implanted with aluminum

A combination of a high-dose (5 s- 10¹⁶ cm^-2) implantation of Al ions into epitaxial n-type 4H SiC layers grown by chemical deposition from th e vapor phase and rapid (15 s) thermal annealing at 1700–1750°C has been used to form layers with a rectangular impurity profile according to the mechanism of solid-phase epitaxial crystallization. The combined effects of enhanced diffusion of radiation defects after implantation and gettering of defects during annealing bring about an improvement in the quality of the initial material, which ensures an increase in the diffusion length of the minority charge carriers by several times. Metastable states annealed within different temperature ranges are formed in SiC under the effect of irradiation with various particles. Low-temperature annealing of radiation defects increases the radiation and temporal lifetime of devices under irradiation. High-temperature annealing of radiation defects makes it possible to vary the lifetime of nonequilibrium charge carriers, i.e, vary the frequency range of devices. The radiation resistance of SiC-based devices increases as the operation temperature is increased to 500°C.     

A microstructural comparison of the initial growth of AlN and GaN layers on basal plane sapphire and sic substrates by low pressure metalorganic chemical vapor deposition

The initial growth by low pressure metalorganic chemical vapor deposition and subsequent thermal annealing of A1N and GaN epitaxial layers on SiC and sapphire substrates is examined using high resolution transmission electron microscopy and atomic force microscopy. Growth under low pressure conditions on sapphire substrates is significantly different from that reported for conventional (atmospheric pressure) conditions. Smooth, single crystal A1N and GaN layers were deposited on sapphire in the initial low temperature (600°C) growth step. Interfacial bonding and not lattice mismatch was found to be the determin ing factor for obtaining good crystallinity for the epitaxial layers as indicated by the growth results on SiC substrates.     

Co/a-GeSi/Ti/Si多层薄膜固相反应外延生长CoSi_2薄膜

研究了在 Co/Ti/Si结构中加入非晶 Ge Si层对 Co Si2 /Si异质固相外延的影响 ,用离子束溅射方法在Si衬底上制备 Co/Ge Si/Ti/Si结构多层薄膜 ,通过快速热退火使多层薄膜发生固相反应。采用四探针电阻仪、AES、XRD、RBS等方法进行测试。实验表明 ,利用 Co/Ge Si/Ti/Si固相反应形成的 Co Si2 薄膜具有良好的外延特性和电学特性 ,Ti中间层和非晶 Ge Si中间层具有促进和改善 Co Si2 外延质量 ,减少衬底耗硅量的作用。Ge原子的存在能够改善外延 Co Si2 薄膜的晶格失配率     

P-Type doping with arsenic in (211)B HgCdTe grown by MBE

Arsenic incorporation and doping in HgCdTe layers grown by molecular beam epitaxy (MBE) were examined in this paper. Arsenic incorporation into MBE-HgCdTe was carried out in two different ways: (1)ex-situ arsenic ion-implantation on indium-doped n-type HgCdTe layers, and (2) through a new approach called arsenic planar doping. We report onex-situ arsenic diffusion on indiumdoped MBE-HgCdTe layers at 450°C. In the investigated layers, arsenic redistribution occurs with a multi-component character. We obtained a diffusion coefficient of D_As = (1-3) × 10⁻¹³ cm²/s at 450°C. Results of differential Hall and fabricated p-n junctions suggest that during high temperature annealing, arsenic preferentially substitutes into Te sublattices and acts as acceptor impurities. In the second case, arsenic has been successfully incorporated during the MBE growth as an acceptor in the planar doping approach. Withoutex-situ annealing, as-grown layers show up to 50% activation of arsenic during the growth. These results are very promising forin-situ fabrication of infrared devices using HgCdTe material.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

基于正交设计的Si基复合衬底优化工艺试验

在正交设计的基础上,通过一系列工艺测试实验,研究了MEE外延温度、MEE退火温度、CdTe外延温度、CdTe退火温度对Si基复合衬底的两个关键质量因素FWHM和表面粗糙度的影响。通过统计技术对测得的实验数据进行了方差分析,结果表明,CdTe退火温度是影响FWHM的关键因子,MEE退火温度和CdTe外延温度对Ra值来说影响是显著的。通过该系列实验得到最优的外延工艺条件。     

Influence of an increase in the implantation dose of erbium ions and annealing temperature on photoluminescence in AlGaN/GaN superlattices and GaN epitaxial layers

Room-temperature photoluminescence (PL) has been studied in AlGaN/GaN superlattices and GaN epitaxial layers implanted with 1-MeV erbium at a dose of 3 × 10¹⁵ cm^?2 and annealed in argon. The intensity of PL from Er³⁺ ions in the superlattices exceeds that for the epitaxial layers at annealing temperatures of 700–1000°C. The strongest difference (by a factor of ～2.8) in PL intensity between the epitaxial layers and the superlattices and the highest PL intensity for the superlattices are observed upon annealing at 900°C. On raising the annealing temperature to 1050°C, the intensity of the erbium emission from the superlattices decreases substantially. This circumstance may be due to their thermal destruction.     

High‐rate deposition of a‐Si:H thin layers for high‐performance silicon heterojunction solar cells

In this paper, we describe a technique for high‐quality interface passivation of n‐type crystalline silicon wafers through the growth of hydrogenated amorphous Si (a‐Si:H) thin layers using conventional plasma‐enhanced chemical vapor deposition. We investigated the onset of crystallization of the a‐Si:H layers at various deposition rates and its effect on the surface passivation properties. Epitaxial growth occurred, even at a low substrate temperature of 90 °C, when the deposition rate was as low as 0·5 Å/s; amorphous growth occurred at temperatures up to 150 °C at a higher deposition rate of 4·2 Å/s. After optimizing the intrinsic a‐Si:H layer deposition conditions and then subjecting the sample to post‐annealing treatment, we achieved a very low surface recombination velocity (7·6 cm/s) for a double‐sided intrinsic a‐Si:H coating on an n‐type crystalline silicon wafer. Under the optimized conditions, we achieved an untextured heterojunction cell efficiency of 16·7%, with a high open‐circuit voltage (694 mV) on an n‐type float‐zone Si substrate. On a textured wafer, the cell efficiency was further enhanced to 19·6%. Copyright © 2011 John Wiley & Sons, Ltd.