双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

SiGeC/Si异质结二极管特性分析与优化设计

基于异质结理论,提出了一种新型p+(SiGeC)-n--n+异质结功率二极管结构。分析了C对SiGe合金的应变补偿作用的物理机理。利用MEDICI模拟、对比分析了C的引入对器件电特性的影响,并针对不同Ge/C组分比进行优化设计。结果表明:在SiGe/Si功率二极管中加入少量的C,在基本不影响器件正向I-V特性和反向恢复特性的前提下,大大减少了器件的反向漏电流,提高了器件稳定性,而且对于一定的Ge含量存在一个C的临界值,使得二极管具有最小的反向漏电流,该临界值的提出,对研究其它结构SiGeC/Si异质结半导体器件有一定的参考意义。     

一种新型SGOI SiGe异质结双极型晶体管

为了改善SiGe异质结双极型晶体管(HBT)的电学特性和频率特性,设计了一种新型的SGOI SiGe HBT。在发射区引入了双轴张应变Si层。多晶Si与应变Si双层组合的发射区有利于提高器件的注入效率。利用Silvaco TCAD软件建立了二维器件结构模型,模拟了器件的工艺流程,并对器件的电学特性和频率特性进行了仿真分析。结果表明,与传统的SiGe HBT相比,新型SGOI SiGe HBT的电流增益β、特征频率fT等参数得到明显改善,在基区Ge组分均匀分布的情况下,β提高了29倍,fT提高了39.9%。     

温度对SiGe/Si异质结功率二极管电学特性的影响(英文)

在考虑到各种物理机制如载流子-载流子散射、俄歇复合、禁带窄化效应及结温效应等的基础上,数值模拟分析了SiGe/Si功率开关二极管的各种温度依赖特性。对Si和SiGe/Si功率二极管而言,温度对器件的正向压降VF、反向击穿电压VB以及反向漏电流JR的影响规律基本相似,即随着温度的升高,正向压降降低,击穿电压增加,反向漏电流迅速提高。然而在相同的温度下,与Si功率开关二极管相比,SiGe/Si二极管(20%Ge含量)的正向压降降低了近0.1V(在正向电流密度10A/cm2的情况下),反向恢复时间缩短了一半以上,反向峰值电流密度也下降了约三分之一,软度因子S提高了2倍多。SiGe二极管的另外一个重要优点是其反向恢复特性受温度影响很小。当温度从300K增加到400K时,Si功率二极管的反向恢复时间增加了近1倍,而SiGe/Si二极管(20%Ge含量)的反向恢复时间基本保持不变。SiGe/Si功率开关二极管的一个缺点是在高温下产生较大的漏电流,但这可以通过适当降低Ge含量来改善。Ge的引入为器件设计提供了更大的自由度,其含量对器件特性有重要影响。为了获得低的正向压降和短的反向恢复时间,应该提高Ge的含量,但Ge含量增加将导致大的漏电流,因此Ge含量的大小应该优化折衷考虑。     

绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性二维数值分析

对绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性进行二维数值分析,研究了该器件的阈值电压特性、转移特性、输出特性.模拟结果表明,随着应变Si1-xGex沟道层中的Ge组分增大,器件的阈值电压向正方向偏移,转移特性增强;当偏置条件一定时,漏源电流的增长幅度随着Ge组分的增大而减小;器件的输出特性呈现出较为明显的扭结现象.     

应变SiGe沟道PMOSFET亚阈值特性模拟

通过简化的模型,对应变SiGe沟道PMOSFET及Si PMOSFET的亚阈值特性作出了简单的理论分析,然后用二维模拟器Medici进行了模拟和对比;研究了截止电流和亚阈值斜率随SiGe PMOSFET垂直结构参数的变化关系。模拟结果同理论分析符合一致,表明应变SiGe沟道PMOSFET的亚阈值特性比Si PMOSFET更差,并且对垂直结构参数敏感,在器件设计时值得关注。     

ZnO/Si异质结中的晶界层行为研究

本文利用电容-电压,电流-电压和深能级瞬态谱研究了ZnO/Si异质结的晶界层行为和载流子的输运机制。当存在高密度界面态时,ZnO/Si异质结的载流子输运受到晶界层的控制。我们观察到了有趣的现象,不同测量温度下得到的ZnO/Si异质结正向lnI-V曲线发生交叉,另外得到ZnO/Si异质结的有效势垒高度随着测量温度的下降而下降,这与理想的异质结热发射模型是相矛盾的。本文的随后各节对上面提到的现象做出解释。     

微波功率SiGe HBT的温度特性

通过研究SiGe异质结双极型晶体管(HBT)的温度特性,发现SiGe HBT的发射结正向电压随温度的变化率小于同质结Si双极型晶体管(BJT).在提高器件或电路热稳定性时,SiGe HBT可以使用比Si BJT更小的镇流电阻.同时SiGe HBT共发射级输出特性曲线在高电压大电流下具有负阻特性,而负阻效应的存在可以有效地抑制器件的热不稳定性效应,从而在温度特性方面证明了SiGe HBT更适合于微波功率器件.     

微波功率SiGe HBT的温度特性

通过研究SiGe异质结双极型晶体管(HBT)的温度特性,发现SiGe HBT的发射结正向电压随温度的变化率小于同质结Si双极型晶体管(BJT).在提高器件或电路热稳定性时,SiGe HBT可以使用比Si BJT更小的镇流电阻.同时SiGe HBT共发射级输出特性曲线在高电压大电流下具有负阻特性,而负阻效应的存在可以有效地抑制器件的热不稳定性效应,从而在温度特性方面证明了SiGe HBT更适合于微波功率器件.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

P型张应变Si/SiGe量子阱红外探测器的能带设计

提出P型张应变Si/SiGe量子阱红外探测器(QWIP)结构,应用k·P方法计算应变Si/SiGe量子阱价带能带结构和应变SiGe合金空穴有效质量.结果表明量子阱中引入张应变使轻重空穴反转,基态为有效质量较小的轻空穴态,因此P型张应变Si/SiGe QWIP与n型QWIP相比具有更低的暗电流;而与P型压应变或无应变QWIP相比光吸收和载流子输运特性具有较好改善.在此基础上讨论了束缚态到准束缚态子带跃迁型张应变p-Si/SiGe QWIP的优化设计.     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.     

Monolithic micropower amplifier using SiGe n-MODFET device

A micropower-relevant model is extracted from the DC characteristics of an n-type buried channel Si/SiGe hetero-junction modulation doped FET (HMODFET). This model is then used to design a novel monolithic SiGe single-stage class-A power amplifier for micropower operation (sub 500 /spl mu/W). The amplifier is fabricated and measured data of the power-gain against operating power are presented for the first time.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

Hot-Carrier and Fowler–Nordheim (FN) Tunneling Stresses on RF Reliability of 40-nm PMOSFETs With and Without SiGe Source/Drain

In this brief, RF reliabilities of hot-carrier and Fowler–Nordheim (FN) tunneling stresses on 40-nm PMOSFETs with and without SiGe source/drain (S/D) are studied and compared in detail. The results show that even the strained device with SiGe S/D has a better RF performance; however, its RF reliabilities after both hot-carrier and FN tunneling stresses are deteriorated remarkably by strain-induced defects. In addition, because the SiGe S/D strain-induced defects are mostly located at the surface of the extension of S/D, but not at the channel, the degradation difference between the strained and nonstrained PMOSFETs becomes less as the stress changes from the hot carrier (gate stress voltage $V_{rm gstr} = hbox{drain stress voltage} V_{rm dstr}$) to the vertical-only, i.e., the FN tunneling stress $(V_{ rm dstr} = hbox{0} hbox{but with some} V_{rm gstr})$.