共查询到18条相似文献,搜索用时 125 毫秒
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系统芯片的可测性设计与测试 总被引:2,自引:0,他引:2
阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。 相似文献
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Verigy 93000 SoC测试系统及测试中偏置电流的实现 总被引:1,自引:0,他引:1
陶新萱 《电子工业专用设备》2011,40(1):4-6
Verigy 93000 SoC测试系统是一个低成本、可扩展的单一测试平台,它是满足SoC全面发展需要的芯片测试系统解决方案.概括介绍了93000自动测试系统(ATE),并讨论了其偏置电流的实现方法. 相似文献
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一种基于嵌入式微处理器内核模块的测试 总被引:3,自引:1,他引:2
基于可复用的嵌入式IP内核模块的系统级芯片(SoC)设计方法使测试面临新的挑战。文章针对IP内核模块测试断面临的技术难点,介绍了IP核模块实现测试所需要构建的硬件环境和通用结构.并以嵌入ARM微处理器棱的SoC为例,提出了具体的测试解决方案。 相似文献
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该文基于65 nm CMOS低漏电工艺,设计了一种用于触摸屏SoC的8通道10位200 kS/s逐次逼近寄存器型(Successive Approximation Register,SAR) A/D转换器(Analog-to-Digital Converter,ADC) IP核。在D/A转换电路的设计上,采用7MSB (Most-Significant-Bit) + 3LSB (Least-Significant-Bit) R-C混合D/A转换方式,有效减小了IP核的面积,并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上,通过采用一种低失调伪差分比较技术,有效降低了输入失调电压。在版图设计上,结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322m267m。在2.5 V模拟电压以及1.2 V数字电压下,当采样频率为200 kS/s,输入频率为1.03 kHz时,测得的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)和有效位数(Effective Number Of Bits,ENOB)分别为68.2 dB和9.27,功耗仅为440W,测试结果表明本文ADC IP核非常适合嵌入式系统的应用。 相似文献
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多IP核复用技术在SoC芯片设计中得到广泛应用,一方面带来设计效率的提高,另一方面由于各类IP核质量参差不齐也造成SoC芯片可靠性的降低,本文着重从微处理器可靠性、IP核通信可靠性、IP核状态检测等方面对多IP复用SoC的可靠性进行了研究。 相似文献
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1前言 模拟/数字信号转换器(ADC)和数字/模拟转换器(DAC)是两种基本的电子应用模块,用于实现模拟和数字信号之间的转换.作为独立器件或者集成到各种混合信号芯片中,广泛的应用于各种电子产品.因此,在对这些混合信号芯片进行测试的时候就要对其中集成的ADC/DAC的性能设计相应的测试方案. 相似文献
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由于要将多种功能融合在单一芯片,使得SoC芯片设计更为复杂,如何降低测试成本成为开发商的当务之急.对此,安捷伦科技半导体测试事业部推出创新概念的93000单一测试平台,提供缩短测试时间、降低测试成本的理想选择,目前全球已经安装了900多套93000系统. 相似文献
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A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%. 相似文献
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Xuan-Lun Huang Jiun-Lang Huang Hung-I Chen Chang-Yu Chen Tseng Kuo-Tsai Ming-Feng Huang Yung-Fa Chou Ding-Ming Kwai 《Journal of Electronic Testing》2012,28(5):705-722
This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC. 相似文献
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This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique. 相似文献
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设计了一种用于多电源SoC的10位8通道1MS/s逐次逼近结构AD转换器。为提高ADC精度,DAC采用改进的分段电容阵列结构。为降低功耗,比较器使用了反相器阈值电压量化器,在模拟输入信号的量化过程中减少静态功耗产生。电平转换器将低电压数字逻辑信号提升为高电平模拟信号。采用UMC 55nm 1P6M数字CMOS工艺上流片验证设计。测试结果表明,当采样频率为1 MS/s、输入信号频率为10 kHz正弦信号情况下,该ADC模块在3.3 V模拟电源电压和1.0 V数字电源电压下,具有最大微分非线性为0.5LSB,最大积分非线性为1LSB。测得的SFDR为75 dB,有效分辨率ENOB为9.27位。 相似文献
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相干光正交频分复用系统(Coherent Optical Orthogonal Frequency Division Multiplexing, CO-OFDM)作为未来高速光通信的重要解决方案,是近年来光传输领域的研究热点。高速CO-OFDM系统需要较高带宽的模数/数模转换器(DAC/ADC),目前技术水平难以达到。文章改进了正交频带复用技术(Orthogonal Band Multiplexing , OBM)的光域实现方案;结合偏振复用技术和偏振分集接收,提出了基于OBM的100Gb/s高速CO-OFDM系统;并对系统传输性能进行数字仿真。结果表明:基于OBM技术的MIMO CO-OFDM系统可有效降低对DAC/ADC的处理速度要求,在不需任何在线色散补偿和偏振控制器件条件下,通过单模光纤传输800km,系统Q值保持在13dB以上。 相似文献
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The wide adoption of third-party hardware Intellectual Property (IP) cores including those from untrusted vendors have raised security concerns for system designers and end-users. Existing approaches to ensure the trustworthiness of individual IPs rarely consider the entire SoC design, especially the IP interactions through SoC bus. These methods can hardly identify malicious logic (or design flaws) distributed in multiple IPs whereas individual IPs fulfill security properties and can pass the security testing/verification. One possible solution is to treat the SoC as one IP core and try to verify security properties of the entire design. This method, however, suffers from scalability issues due to the large size of SoC designs with multiple IP cores integrated. In this paper, we present a scalable SoC bus verification framework trying to verify the security properties of SoC bus implementation where the bus protocol plays the role of the golden reference. More specifically, finite state machine (FSM) models will be constructed from the bus implementation and the trustworthiness will be verified based on the property set derived from the bus protocol and potential security threats. Along with IP level formal verification solutions, the proposed framework can help ensure the security of large-scale SoCs. Experimental results on ARM AMBA Bus demonstrate that our approach is applicable and scalable to prevent information leakage and denial-of-service (DoS) attack by verifying security properties. 相似文献