基于门控时钟的低功耗MCU的设计与实现

文章研究了一种基于门控时钟的低功耗MCU的设计与实现，详细阐述了门控时钟的实现机制，以及为避免引入诱导噪声所采取的措施。经过Power Compiler分析和VCS仿真，使这种基于门控时钟的低功耗MCU在性能几乎没有损失的情况下，降低了5％—15％的功耗，而芯片面积仅增加4％。最后，采用TSMC 0．35um CMOS工艺实现了该低功耗MCU。     

SoC低功耗设计及其技术实现

文章根据低功耗设计理论和方法,分别从系统级、模块级及RTL级三个层次上考虑一款SoC芯片功耗设计。在系统级采用工作模式管理方式,在模块级采用软件管理的方式,RTL级采用门控方式,三种方式的应用大大降低芯片了的功耗。仿真分析表明,该芯片的低功耗设计策略取得了预期的效果,实现了较低的动态功耗与很低的静态功耗。该SoC采用0．18μm CMOS工艺库实现,面积为7．8mm×7．8mm,工作频率为80Mnz,平均功耗为454．268mW。     

基于CPF格式的多电压芯片设计

集成电路进入SoC时代以来,功耗已经成为与面积和性能同等重要的设计目标,在无线、移动和嵌入式应用中,功耗指标已经成为最重要的因素之一.本文概述了多电压设计的概念,设计中的注意事项,以Cadence公司CPF格式定义电压转换器,采用1 30nm多电压工艺库进行了芯片设计.结果表明,芯片中采用多电压设计技术可以有效的降低芯片的动态功耗.     

一种低功耗结构的ADC设计

逐次逼近结构ADC是中速中高分辨率应用中的常见结构,其中DAC多采用电容阵列结构,但其动态功耗随分辨率的增加而增加.论文设计了一种新颖的10位ADC结构,它采用两级进行模数转换的方法,高位采用低功耗的并行模数转换结构,低位采用逐次逼近模数转换结构,通过合理设计高低位转换位数、低功耗比较器,采用简单的二进制搜索算法,有效...     

基于OPF格式的多电压芯片设计

集成电路进入SoC时代以来,功耗已经成为与面积和性能同等重要的设计目标,在无线、移动和嵌入式应用中,功耗指标已经成为最重要的因素之一。本文概述了多电压设计的概念,设计中的注意事项,以Cadence公司CPF格式定义电压转换器,采用130nm多电压工艺库进行了芯片设计。结果表明,芯片中采用多电压设计技术可以有效的降低芯片的动态功耗。     

片上二级cache漏流功耗控制策略研究

 随着工艺尺寸缩小和处理器频率的提高,大容量的片上L2 cache成为处理器漏流功耗的主要来源.提出的保守多状态(C-SP&;SD)和推断多状态(S-SP&;SD)两种L2 cache漏流功耗控制策略能够将状态保留(State-Preserving)与状态破坏(State-Destroying)两种低功耗模式相结合.如果一个数据在多级cache存储层次中存在多个副本,那么只保留一个副本处于活跃状态,其他副本均被转换到低功耗模式,并且在不显著影响处理器性能的前提下尽可能转换到更低功耗的状态破坏模式.与传统的L2 cache漏流控制策略相比,C-SP&;SD策略以较小的处理器性能损失换取较大的L2 cache漏流功耗节省,而S-SP&;SD策略则实现了最优的L2 cache漏流功耗节省和处理器能量效率.     

多核处理器功耗优化与评估技术发展综述

多核处理器已经成为当前处理器设计的主流,其并行处理能力显著提高了处理器的性能,同时,多核处理器本身的高度集成度也使其功耗显著上升,从而在一定程度上限制了多核处理器的发展。本文描述了低功耗设计的基本理论、常用的低功耗设计技术和多核处理器中的功耗评估技术,并分析和总结了低功耗多核处理器研究的最新进展,可为多核处理器的设计提供有益的参考。     

数字集成电路低功耗优化设计解析

在集成电路制造技术发展的推动下,芯片的集成度与速度持续提高,但单面面积的功耗却呈上升趋势.目前,一切IC设计都十分关注功能问题,并积极寻求路径优化功耗设计.在本案,笔者结合工作经验,浅析数字集成电路低功耗的优化设计.     

基于SoC低功耗MMC卡控制器的设计

本文基于最新的MMC4.1协议,设计了一款基于AHB总线的低功耗MMC卡控制器.设计采用了高性能改进异步FIFO.针对MMC卡常用于便携式产品中的低功耗需求,采用了动态功耗管理和门控时钟技术,可降低功耗约60%;探讨了一种基于SoC高性能接口控制器电路通用体系架构,已成功应用到多种接口控制器的设计中.设计通过了仿真(NC-Verilog)、综合(DC)以及FPGA验证,嵌入到单板系统中,实现了与MMC存储卡之间的数据传输.     

超深亚微米数字电路的低功耗设计

随着集成电路逻辑复杂度日益提高,而工艺尺寸进入了超深亚微米数量级,低功耗设计已经成为整个SOC设计中关键的问题之一.电源电压是影响功耗的最重要因素,而阈值电压、体偏压和时钟频率也对功耗有影响.目前,对于数字电路,已经研发出一些有效地进行功耗管理,降低功耗的技术,并已应用于具体项目中.本文首先综述性地介绍几种低功耗设计方法,包括:多阈值电压CMOS技术;多电源电压;门控时钟;动态电压频率调制;动态体偏压调制;加入电源门控、以及状态可保持的电源门控技术,并逐一讨论了它们对降低功耗的具体作用.最后,针对最新的基于通用功耗格式的状态保持电源门控技术,本文概述其实现步骤.     

一种多处理器原型及其系统芯片设计方法

 随着嵌入式应用快速发展,系统芯片(SoC)设计日趋复杂.高效可靠的设计多处理器系统芯片逐渐成为一个巨大挑战.本文提出一种多处理器原型及其SoC设计方法,将多处理器及其通信统一建模于一个多层次、灵活和可配的软硬件原型中,通过分层次、从高层抽象到底层实现逐步深入的方法解决软硬件接口验证问题和完善软硬件架构.H.264解码实验证明多处理器原型功能可行性和物理可实现性.基于该原型的多层次细化方法可有效确保SoC软硬件设计的正确性,并有助于软硬件结构协同设计优化.     

CMOS数字电路低功耗的层次化设计

随着芯片上可以集成越来越多的管子,电路规模在不断扩大,工作频率在不断提高,这直接导致芯片功耗的迅速增长,无论是从电路可靠性来看,还是从能量受限角度来讲,低功耗都已成为CMOS数字电路设计的重要内容。由于不同设计抽象层次对电路功耗的影响不同,对各有侧重的低功耗设计方法和技术进行了讨论,涉及到工艺,版图,电路,逻辑,结构,算法和系统等不同层次。在实际设计中,根据具体应用环境,综合不同层次全面考虑功耗问题,可以明显降低电路功耗。     

Framework for thermal-aware verification of digital and mixed signal systems

The evolution of the semiconductor manufacturing allows the integration of more features, such as transistors, onto a single die which further increases the complexity of the chips and introduces new design challenges at each process node. Power density has reached the limits of available cooling solutions, thus thermally-aware design decisions are needed early in the design process. Co-simulating the logic function and thermal behavior of the design can help to evaluate the performance of the system at various higher abstraction levels across the different stages of the design process. Logi-thermal simulators use the switching activities of the system to predict the dissipated power and from that calculate the temperature distribution across the chip. The temperature dependence of certain parameters (such as delay) and temperature sensitive analog/mixed signal components can also be considered during the co-simulation. This paper presents a thermal-aware co-simulation environment to allow the temperature effects to be considered in various steps in the mixed signal SoC design flow.     

Power consumption reduction in systems on Chip (SoCs)

Systems on Chip are becoming extremely complex integrated circuits, containing tens or hundreds of analog,rf and digital blocks. For most applications, they have to present extremely low power consumption. It is the case, for instance, in ad hoc networks for which 100 or 1000 SoC nodes have to sense their environment, do some processing and send by radio some information to adjacent nodes in a multi-hop fashion to reach finally a base station. The design of such SoC nodes, to achieve the required extremely low power consumption, has to performed first at the system level, including low power communication protocols and data routing through the network, node wake-up strategies, low-power software and operating systems, innovative solutions for the sensor part, flexible or reconfigurable and very low power digital processing, low-power networks on chip for the communication between embedded processors and memories, as well as low powerrf front-ends. In addition, due to the impressive technology pace, new problems have to be solved for the design of SoCs, such as the interconnect delays, reliability and the dramatic increase of the static power. Some techniques, considered as the most efficient, of dynamic as well as static power reduction are described. It is however shown that the design of SoCs in 130 nm and below will impact dramatically the design methodologies, mainly due the static power increase. Finally, if today most SoCs are powered by batteries, alternative sources of energy are reviewed.     

Cosimulation-based power estimation for system-on-chip design

We present efficient power estimation techniques for hardware-software (HW-SW) system-on-chip (SoC) designs. Our techniques are based on concurrent and synchronized execution of multiple power estimators that analyze different parts of the SoC (we refer to this as coestimation), driven by a system-level simulation master. We motivate the need for power coestimation, and demonstrate that performing independent power estimation for the various system components can lead to significant errors in the power estimates, especially for control-intensive and reactive-embedded systems. We observe that the computation time for performing power coestimation is dominated by: i) the requirement to analyze/simulate some parts of the system at lower levels of abstraction in order to obtain accurate estimates of timing and switching activity information and ii) the need to communicate between and synchronize the various simulators. Thus, a naive implementation of power coestimation may be too inefficient to be used in an iterative design exploration framework. To address this issue, we present several acceleration (speed-up) techniques for power coestimation. The acceleration techniques are energy caching, software power macro-modeling, and statistical sampling. Our speed-up techniques reduce the workload of the power estimators for the individual SoC components, as well as their communication/synchronization overhead. Experimental results indicate that the use of the proposed acceleration techniques results in significant (8/spl times/ to 87/spl times/) speed-ups in SOC power estimation time, with minimal impact on accuracy. We also show the utility of our coestimation tool to explore system-level power tradeoffs for a TCP/IP check-sum engine subsystem.     

系统芯片的关键技术及发展方向

系统芯片,即(SoC),将包含处理器、存储器和片上逻辑等的一个系统集成在单一的芯片上。SoC所特有的功能强、速度高、体积小、成本低、功耗低等优点使得其技术不断发展,应用越来越广泛。文章首先探讨了系统芯片(SoC)的特点及分类,接着详细阐述了开发SoC所需IP核设计与复用、软硬件协同设计、软硬件协同设计等关键技术。分析了基于平台设计方法的优点,并介绍了SoC的一体化测试流程、共时测试等SoC测试新技术。     

一种极低功耗的CMOS带隙基准源

随着SoC在便携产品中应用的迅猛发展,低功耗技术变得越来越重要。本文采用了0.18um的标准CMOS工艺来,设计了一种无电阻、工作在亚阈值区的低功耗、小面积的CMOS电压基准源。这个带隙基准可以灵活运用于极低功耗的SoC系统中。这个电路的电源电流大约为150nA,可以在1.5V～3.3V之间的电源电压下工作,基准源的输出电压的线性度为44.4ppm/V。当电源电压为1.5V,室温下带隙基准电路的输出电压为1.1126V,100Hz频率下的电源抑制比为-66dB,当温度在-20℃与80℃之间变化时,输出电压的温度系数是55ppm/℃。整个带隙基准的芯片面积是0.011mm2。