N型6H-SiCMOS电容的电学特性

在可商业获得的 N型 6 H- Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,制备 MOS电容 .详细测量并分析了 6 H- Si C MOS电容的电学特性 ,其有效电荷密度为 4.3× 10 1 0 cm- 2 ;Si C与 Si O2 之间的势垒高度估算为 2 .6 7e V;Si C热生长 Si O2 的本征击穿场强 (用累计失效率 5 0 %时的场强来计算 )为 12 .4MV/ cm ,已达到了制作器件的要求 .     

6H-SiC高反压台面pn结二极管

在可商业获得的单晶 6 H- Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ;并在此 6 H - Si C结构材料上 ,利用反应离子刻蚀和接触合金化技术 ,制作台面 pn结二极管 .详细测量并分析了器件的电学特性 ,测量结果表明此 6 H - Si C二极管在室温、空气介质中 ,- 10 V时 ,漏电流密度为 2 .4× 10 - 8A/cm2 ,在反向电压低于 6 0 0 V及接近30 0℃高温下都具有良好的整流特性 .     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器件样品 .测试结果表明 ,当沟道长度为 2μm时 ,Si/ Si Ge PMOS器件的跨导为 45 m S/ mm(30 0 K)和 92 m S/ mm (77K) ,而相同结构的全硅器件跨导则为 33m S/ mm (30 0 K)和 39m S/ m m (77K) .     

一种新型的6H-SiC MOS器件栅介质制备工艺

采用干 O2 +CHCCl3(TCE)氧化并进干 /湿 NO退火工艺生长 6H-Si C MOS器件栅介质 ,研究了 Si O2 /Si C界面特性。结果表明 ,NO退火进一步降低了 Si O2 /Si C的界面态密度和边界陷阱密度 ,减小了高场应力下平带电压漂移 ,增强了器件可靠性 ,尤其是湿 NO退火的效果更为明显。     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟,给出了以提高跨导为目标的Si/SiGe PMOSFET优化设计方法,包括栅材料的选择、沟道层中Ge组分及其分布曲线的确定、栅氧化层及Si盖帽层厚度的优化和阈值电压的调节,基于此已研制出Si/SiGe PMOSFET器件样品.测试结果表明,当沟道长度为2μm时,Si/SiGe PMOS器件的跨导为45mS/mm(300K)和92mS/mm(77K),而相同结构的全硅器件跨导则为33mS/mm(300K)和39mS/mm(77K).     

含氟超薄栅氧化层的抗击穿特性研究

对含 F超薄栅氧化层的击穿特性进行了实验研究。实验结果表明 ,在栅介质中引入适量的 F可以明显地提高栅介质的抗击穿能力。分析研究表明 ,栅氧化层的击穿主要是由于正电荷的积累造成的 ,F的引入可以对 Si/Si O2 界面和 Si O2 中的 O3 ≡ Si·与 Si3 ≡ Si·等由工艺引入的氧化物陷阱和界面陷阱进行补偿 ,从而减少了初始固定正电荷和 Si/Si O2 界面态 ,提高了栅氧化层的质量。研究结果表明 ,器件的击穿电压与氧化层面积有一定的依赖关系 ,随着栅氧化层面积的减小 ,器件的击穿电压增大。     

碳化硅CMOS反相器的特性

建立了6 H- Si C CMOS反相器的电路结构和物理模型,并利用MEDICI软件对其特性进行了模拟.研究了Si C CMOS反相器的温度特性,结果表明,室温下沟道长度为1.5 μm的6 H- Si C CMOS反相器的阈值电压、高电平噪声容限和低电平噪声容限分别为1.6 5 7,3.15 6和1.4 70 V,且随着温度的升高而减小.     

离子注入4H-SiC MESFET器件的夹断电压

考虑离子注入沟道和沟道深度的影响,提出了精确的离子注入4 H- Si C MESFET器件夹断电压的理论计算方法.注入浓度由蒙特卡罗模拟软件TRIM提取计算.研究了温度、外延层受主浓度、注入离子激活率对夹断电压的影响.     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6 H- Si C肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

硅熔体中3C-SiC的生长及6H-SiC晶型的抑制

论述了从硅熔体中生长 3C- Si C晶体过程中 6 H- Si C晶型控制的一般原理 .采用将硅置于高纯石墨坩埚中使其在高温条件下熔化 ,坩埚内壁石墨自然熔解于硅熔体中形成碳饱和的硅熔体 ,在石墨表面形成厚约 0 .2 m m的Si C薄层 .X射线衍射 (XRD)、X射线光电子能谱 (XPS)、Ram an散射等分析表明所制备样品为 3C- Si C多晶体 .实验结果进一步证明从硅熔体中生长 3C- Si C晶体过程中 ,通过适当调整工艺参数可以抑制 6 H- Si C晶型的形成 .     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

UHF频段高功率SiC SIT

采用导通SiC衬底上的SiC多层外延材料,成功制作出了国内首个SiC SIT(静电感应晶体管).该器件研制中,采用了自对准工艺、高能离子注入及高温退火工艺、密集栅深凹槽干法刻蚀工艺、PECVD SiO:和SizNy介质钝化工艺,有效抑制了漏电并提高了器件击穿电压,器件功率输出能力由此得到提升.最终28 cm栅宽SiC ...     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

Degradation of AlGaN/GaN HEMTs under elevated temperature lifetesting

Elevated temperature lifetesting was performed on 0.25 μm AlGaN/GaN HEMTs grown by MOCVD on 2-in. SiC substrates. A temperature step stress (starting at T_a of 150 °C with a step of 15 °C; ending at T_a of 240 °C; 48 h for each temperature cycle) was employed for the quick reliability evaluation of AlGaN/GaN HEMTs. It was found that the degradation of AlGaN/GaN HEMTs was initiated at ambient temperature of 195 °C. The degradation characteristics consist of a decrease of drain current and transconductance, and an increase of channel-on-resistance. However, there is no noticeable degradation of the gate diode (ideality factor, barrier height, and reverse gate leakage current). The FIB/STEM technique was used to examine the degraded devices. There is no detectable ohmic metal or gate metal interdiffusion into the epitaxial materials. Accordingly, the degradation mechanism of AlGaN/GaN HEMTs under elevated temperature lifetesting differs from that observed in GaAs and/or InP HEMTs. The reliability performance was also compared between two vendors of AlGaN/GaN epilayers. The results indicate that the reliability performance of AlGaN/GaN HEMTs could strongly depend on the material quality of AlGaN/GaN epitaxial layers on SiC substrates.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

S波段连续波SiC功率MESFET

利用国产SiC外延材料和自主开发的SiC器件工艺加工技术,实现了SiC微波功率器件在S波段连续波功率输出大于10W、功率增益大于9dB、功率附加效率不低于35%的性能样管,初步显现了SiC器件在S波段连续波大功率、高增益方面的优势。与以往的硅微波功率器件相比,在同样的频率和输出功率下,SiC微波功率器件的体积不到Si器件的1/7,重量不到Si器件的20%,其功率增益较Si器件提高了3dB以上,器件效率也得到了相应的提高。同时由于SiC微波功率器件的输入、输出阻抗要明显高于Si微波功率器件,在一定程度上可以简化或不用内匹配网络来得到比较高的微波功率增益,这就为器件的小体积、低重量奠定了基础,也为器件的大功率输出创造了条件。     

Current SiC technology for power electronic devices beyond Si

Recent big progress in SiC technology for power electronic devices beyond Si is reviewed. Historical aspects in SiC development are described. Current subjects such as bulk crystal growth, epitaxial growth, device processes for new generation of SiC power devices are briefly explained. Commercially available Schottky diodes and possible switching devices are introduced.     

高温氧化对SiC MOS器件栅氧可靠性的影响

SiC金属氧化物半导体(MOS)器件中SiO2栅氧化层的可靠性直接影响器件的功能.为了开发高可靠性的栅氧化层,将n型4H-SiC (0001)外延片分别在1 200,1 250,1 350,1 450和1 550℃5种温度下进行高温干氧氧化实验来制备SiO2栅氧化层.在室温下,对SiC MOS电容样品的栅氧化层进行零时击穿(TZDB)和与时间有关的击穿(TDDB)测试,并对不同干氧氧化温度处理下的栅氧化层样品分别进行了可靠性分析.结果发现,在1 250℃下进行高温干氧氧化时所得的击穿场强和击穿电荷最大,分别为11.21 MV/cm和5.5×10-4 C/cm2,势垒高度(2.43 eV)最接近理论值.当温度高于1 250℃时生成的SiO2栅氧化层的可靠性随之降低.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V 碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V 碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0 V),出现更严重的电学性能退化。利用中带电压法分析发现,栅极偏置下氧化层内的垂直电场提升了陷阱电荷的生成率,加剧了阈值电压的退化。中子位移损伤会导致SiC JBS二极管的正向电流和反向电流减小。在漏极偏置下进行中子位移损伤效应实验,SiC MOSFET的电学性能退化最严重。该研究为空间用SiC器件的辐射效应机理及抗辐射加固研究提供了一定的参考和支撑。     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V