An Ultra-low-power Area-efficient Non-volatile Memory in 0.18μm Single-poly CMOS Process

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm² and 0.12 mm², respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V. The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18μm standard CMOS process

This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor,an RF/analog front-end circuit,an NVM memory and a digital baseband in a standard CMOS process.The sensor with a low power sigma-delta(ΣΔ) ADC is designed to operate in low and high resolution modes.It can not only achieve the target accuracy but also reduce the power consumption and the sensing time.A CMOS-only RF rectifier and a single-poly non-volatile memory(NVM) are designed to realize a low cost tag chip.The 192-bit-N VM tag chip with an area of 1 mm~2 is implemented in a 0.18-μm standard CMOS process.The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled.It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP.The inaccuracy of the sensor is -0.6℃/0.5℃(-1.0℃/1.2℃) in the operating range from 5 to 15℃in high resolution mode(-30 to 50℃in low resolution mode).The resolution of the sensor achieves 0.02℃(0.18℃) in high(low) resolution mode.     

可垂直集成的无电容式动态存储器件

A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.     

一种面积紧凑的视觉芯片处理单元存储器

This paper presents a novel compact memory in the processing element （PE） for single-instruction multiple-data （SIMD） vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.     

基于反熔丝结构的低成本嵌入式一次可编程4-kbit 存储器宏

A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.     

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.     

A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μm~2.Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps.At a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.     

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

正A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory(NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.     

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS

This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm~2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

Low-noise sub-harmonic injection locked multiloop ring oscillator

A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μm 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of -112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology.     

A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

A transformer-based CMOS power amplifier（PA） is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter.The third harmonic of the power stage and driver stage can be cancelled out in a specific power region.The two-stage PA fabricated in a standard 0.18μm CMOS process delivers 27.5 dBm with 27%PAE at the 1-dB compression point(P_1dB) and offers 21 dB gain.The PA achieves 5.5%EVM and meets the spectrum mask at 20.5 dBm average power.Another conventional PA with a zero-cross-point of g_m3 bias is also fabricated and compared to prove its good linearity and efficiency.     

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler(DMP).Here,a new combination of DFF has been introduced in the DMP.By means of the cooperation and coordination among three types,DFF, SCL,TPSC,and CMOS static flip-flop,the DMP demonstrates high speed,wideband,and low power consumption with low phase noise.The chip has been fabricated in a 0.18-μm CMOS process of SMIC.The measured results show that the DMP’s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier.The core area of the die without PAD is 57×30μm~2.Due to its excellent performance,the DMP could be applied to a PLL-based frequency synthesizer for many RF systems,especially for multi-standard radio applications.     

一种新型的FPGA芯片FDP2008

A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX ＋ Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 ×30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.     

应用于CMOS图像传感器中带有失调电压消除功能的电容比值非相关十位循环式模数转换器

A 10-bit ratio-independent switch-capacitor（SC） cyclic analog-to-digital converter（ADC） with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio（SNDR） of 53.6 dB and a DNL of C0：12/0：14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.     

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

Power dissipation,speed and stability are the most important parameters for multiple-valued SRAM design.To reduce the power consumption and further improve the performance of the ternary SRAM cell,we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors (CNFETs).The performance is simulated in terms of three criteria including standby-power,delay (write and read) and stability (RSNM).Compared to the novel ternary SRAM cell,our results show that the average standby-power,write and read delay of the proposed cell are reduced by 78.1％,39.6％ and 58.2％,respectively.In addition,the RSNM under process variations is 2.01 × and 1.95× of the conventional and novel ternary SRAM cells,respectively.     

Comparative analysis of memristor models and memories design

The advent of the memristor breaks the scaling limitations of MOS technology and prevails over emerging semiconductor devices.In this paper,various memristor models including behaviour,spice,and experimental are investigated and compared with the memristor's characteristic equations and fingerprints.It has brought to light that most memristor models need a window function to resolve boundary conditions.Various challenges of availed window functions are discussed with matlab's simulated results.Biolek's window is a most acceptable window function for the memristor,since it limits boundaries growth as well as sticking of states at boundaries.Simmons tunnel model of a memristor is the most accepted model of a memristor till now.The memristor is exploited very frequently in memory designing and became a prominent candidate for futuristic memories.Here,several memory structures utilizing the memristor are discussed.It is seen that a memristor-transistor hybrid memory cell has fast read/write and low power operations.Whereas,a 1T1R structure provides very simple,nanoscale,and non-volatile memory that has capabilities to replace conventional Flash memories.Moreover,the memristor is frequently used in SRAM cell structures to make them have non-volatile memory.This paper contributes various aspects and recent developments in memristor based circuits,which can enhance the ongoing requirements of modem designing criterion.     

An effective timing characterization method for an accuracy-proved VLSI standard cell library

This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.     

抗DPA攻击的功耗平衡SRAM设计

A power balance static random-access memory(SRAM) for resistance to differential power analysis(DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm~2.The post-simulation results show that the normalized energy deviation(NED) and normalized standard deviation(NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.     

采用电压复位技术的像素级模数转换器

This paper presents a 50 Hz 15-bit analog-to-digital converter(ADC) for pixel-level implementation in CMOS image sensors.The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets.The core circuit for charge/pulse conversion is specially optimized for low power,low noise and small area.An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification.The measurement result shows a standard deviation of 1.8 LSB for full-scale output.The ADC has an area of 4545 m2 and consumes less than 2 W in a standard 1P-6M 0.18 m CMOS process.