An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18μm standard CMOS process

This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor,an RF/analog front-end circuit,an NVM memory and a digital baseband in a standard CMOS process.The sensor with a low power sigma-delta(ΣΔ) ADC is designed to operate in low and high resolution modes.It can not only achieve the target accuracy but also reduce the power consumption and the sensing time.A CMOS-only RF rectifier and a single-poly non-volatile memory(NVM) are designed to realize a low cost tag chip.The 192-bit-N VM tag chip with an area of 1 mm~2 is implemented in a 0.18-μm standard CMOS process.The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled.It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP.The inaccuracy of the sensor is -0.6℃/0.5℃(-1.0℃/1.2℃) in the operating range from 5 to 15℃in high resolution mode(-30 to 50℃in low resolution mode).The resolution of the sensor achieves 0.02℃(0.18℃) in high(low) resolution mode.     

一种面积紧凑的视觉芯片处理单元存储器

This paper presents a novel compact memory in the processing element （PE） for single-instruction multiple-data （SIMD） vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.     

可垂直集成的无电容式动态存储器件

A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.     

基于反熔丝结构的低成本嵌入式一次可编程4-kbit 存储器宏

A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.     

A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

This paper presents a new dual Vt 8T SRAM cell having single bit-line read and write,in addition to Write Assist and Read Isolation (WARI).Also a faster write back scheme is proposed for the half selected cells.A high Vt device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write.The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read.Static noise margins for data read (RSNM),write (WSNM),read delay,write delay,data retention voltage (DRV),leakage and average powers have been calculated.The proposed cell was found to operate properly at a supply voltage as small as 0.41 V.A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay,pulse timing hardware requirements and power consumption.The proposed new WARI 8T cell shows better performance in terms of easier write,improved read noise margin,reduced leakage power,and less delay as compared to the existing schemes that have been available so far.It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.     

应用于CMOS图像传感器中带有失调电压消除功能的电容比值非相关十位循环式模数转换器

A 10-bit ratio-independent switch-capacitor（SC） cyclic analog-to-digital converter（ADC） with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio（SNDR） of 53.6 dB and a DNL of C0：12/0：14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.     

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

正A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory(NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.     

A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS

A new loading-balanced architecture for high speed and low power consumption pipeline analog-to-digital converter (ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system''s point of view, all load capacitors of the shared OTAs are balanced by employing a loading-balanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm². The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio (SNDR) and 62.97 dB spurious-free dynamic range (SFDR) with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 mW at 200 MS/s from a 1.8 V supply.     

抗DPA攻击的功耗平衡SRAM设计

A power balance static random-access memory(SRAM) for resistance to differential power analysis(DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm~2.The post-simulation results show that the normalized energy deviation(NED) and normalized standard deviation(NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.     

一种应用于直接变频系统的低功耗混合信号直流失调消除电路

A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm².     

一种用于3-5GHz IR-UWB的0.18um CMOS BPSK 调制发射机

This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system. It is based on up-conversion with a high linearity passive mixer. Unlike the traditional BPSK modulation scheme, the local oscillator (LO) is modulated by the baseband data instead of the pulse. The chip is designed and fabricated by standard 0.18 μ m CMOS technology. The transmitter achieves a high data rate up to 400 Mbps. The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier. The maximum peak-to-peak amplitude of the pulse is 600 mV. It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate. The energy efficiency is 91.4 pJ/pulse. The die area is 1.4 × 1.4 mm².     

应用于生物医疗的0.6-V 8.3-ENOB 异步时序逐次逼近型模数转换器

A microwatt asynchronous successive approximation register （SAR） analog-to-digital converter （ADC） is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power require- ments of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.     

Comparative analysis of memristor models and memories design

The advent of the memristor breaks the scaling limitations of MOS technology and prevails over emerging semiconductor devices.In this paper,various memristor models including behaviour,spice,and experimental are investigated and compared with the memristor's characteristic equations and fingerprints.It has brought to light that most memristor models need a window function to resolve boundary conditions.Various challenges of availed window functions are discussed with matlab's simulated results.Biolek's window is a most acceptable window function for the memristor,since it limits boundaries growth as well as sticking of states at boundaries.Simmons tunnel model of a memristor is the most accepted model of a memristor till now.The memristor is exploited very frequently in memory designing and became a prominent candidate for futuristic memories.Here,several memory structures utilizing the memristor are discussed.It is seen that a memristor-transistor hybrid memory cell has fast read/write and low power operations.Whereas,a 1T1R structure provides very simple,nanoscale,and non-volatile memory that has capabilities to replace conventional Flash memories.Moreover,the memristor is frequently used in SRAM cell structures to make them have non-volatile memory.This paper contributes various aspects and recent developments in memristor based circuits,which can enhance the ongoing requirements of modem designing criterion.     

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.     

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum ⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm² including pads.     

A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μm~2.Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps.At a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.     

一种应用于RFID标签的新型功率放大器设计

A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm² in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm².     

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage.In this technique,a negative bit-line voltage is applied to one of the write bit-lines,while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell.Supply voltage to one of the inverters is interrupted to weaken the feedback.Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time.Amount of boosting required for write performance improvement is also reduced due to feedback weakening,solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques.The proposed design improves write time by 79％,63％ and slower by 52％ with respect to LP 10 T,WRE 8 T and 6 Tcells respectively.It is found that write margin for the proposed cell is improved by about 4×,2.4× and 5.37× compared to WRE8 T,LP10 T and 6 T respectively.The proposed cell with boosted negative bit line (BNBL) provides 47％,31％,and 68.4％ improvement in write margin with respect to no write-assist,negative bit line (NBL) and boosted bit line (BBL) write-assist respectively.Also,new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results.All simulations are done on TSMC 45 nm CMOS technology.