MOS AlGaN/GaN HEMT研制与特性分析

研制出在蓝宅石衬底上制作的MOS AIGaN/GaN HEMT.器件栅长1um,源漏间距4um,采用电子束蒸发4nm的Si02做栅介质.在4V栅压下器件饱和电流达到718mA/mm,最大跨导为172mS/mm,ft和fmax分别为8.1和15.3GHz.MOS HEMT栅反向泄漏电流与未做介质层的肖特基栅相比,在反偏10V时由2.1×10-8mA/mm减小到8.3×10-9mA/mm,栅漏电流减小2个数量级.MOS AIGaN/GaN HEMT采用薄的栅介质层,在保证减小栅泄漏电流的同时未引起器件跨导明显下降.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

90nm工艺下nMOS器件最大衬底电流应力特性

研究了90nm工艺条件下的轻掺杂漏(lightly-doped drain,LDD)nMOSFET器件最大衬底电流应力特性.在比较分析了连续不同电应力后LDD nMOSFET的GIDL(gate-induced drain leakage)电流变化后,发现当器件的栅氧厚度接近1nm,沟长接近100nm时,最大衬底电流应力不是电子注入应力,也不是电子和空穴的共同注入应力,而是一种空穴注入应力,并采用空穴应力注入实验、负最大衬底电流应力实验验证了这一结论.     

90nm工艺下nMOS器件最大衬底电流应力特性

研究了90nm工艺条件下的轻掺杂漏(lightly-doped drain,LDD)nMOSFET器件最大衬底电流应力特性.在比较分析了连续不同电应力后LDD nMOSFET的GIDL(gate-induced drain leakage)电流变化后,发现当器件的栅氧厚度接近1nm,沟长接近100nm时,最大衬底电流应力不是电子注入应力,也不是电子和空穴的共同注入应力,而是一种空穴注入应力,并采用空穴应力注入实验、负最大衬底电流应力实验验证了这一结论.     

GIDL current degradation in LDD nMOSFET under hot hole stress

The degradation of gate-induced drain leakage（GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter I_DIFF.I_DIFF is the difference of GIDL currents measured under two conditions of drain voltage V_D=1.4 V and gate voltage V_G=-1.4 V while V_DG is fixed.After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region.These trapped holes diminishΔE_X which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make I_DIFF lessening.I_DIFF extracted from GIDL currents decreases with increasing stress time t.The degradation shifts of I_DIFF,MAX(ΔI_DIFF,MAX) follows a power law against t:ΔI_DIFF,MAX∝t^m, m= 0.3.Hot electron stress is performed to validate the related mechanism.     

Characteristics of AlGaN/GaN/AlGaN double heteroj unction HEMTs with an improved breakdown voltage

正We studied the performance of AlGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with an AlGaN buffer layer,which leads to a higher potential barrier at the backside of the twodimensional electron gas channel and better carrier confinement.This,remarkably,reduces the drain leakage current and improves the device breakdown voltage.The breakdown voltage of AlGaN/GaN double heterojunction HEMTs (~ 100 V) was significantly improved compared to that of conventional AlGaN/GaN HEMTs(~50 V) for the device with gate dimensions of 0.5 x 100μm and a gate-drain distance of 1μm.The DH-HEMTs also demonstrated a maximum output power of 7.78 W/mm,a maximum power-added efficiency of 62.3%and a linear gain of 23 dB at the drain supply voltage of 35 V at 4 GHz.     

“100kt／a以下规模裂解炉改造方案研究”通过总部科技开发部组织的鉴定

由中国石化工程建设公司、北京化工研究院、南京工业炉设计研究所、中国石化齐鲁股份有限公司、中国石油化工股份有限公司天津分公司等五个单位共同承担的集团公司科研项目“100kt／a以下规模裂解炉改造方案研究）”6月16日在北京通过总部科技开发部组织的技术鉴定，集团公司科技委常务副主任、工程院院士袁晴棠主持了鉴定会，总部有关部门以及来自各生产企业的20名专家参加了鉴定会。     

Analysis of AIGaN/GaN high electron mobility transistors failure mechanism under semi-on DC stress

Semi-on DC stress experiments were conducted on A1GaN/GaN high electron mobility transistors （HEMTs） to find the degradation mechanisms during stress. A positive shift in threshold voltage （VT） and an increase in drain series resistance （RD） were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in Vx is the main factor leading to the degradation of saturation drain current （IDs）, while the increase in RD results in the initial degradation of Ios in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the A1GaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate-drain access region induced by the hot electron effect accounts for the increase in RD.     

Ka波段360度低损耗模拟移相器

在本文中,我们提出了一种新的反射型宽带360度MMIC模拟移相器。该移相器是基于矢量合成理论设计的,由三个Lange耦合器组成,制作工艺为标准的0.25微米GaAs工艺。我们采用4个4×40微米的GaAs HEMT作为反射负载。为了抵消器件的寄生电容,我们将一条起电感作用的微带线与器件并联,使得反射负载表现为纯阻性,并同时减小了移相器的插入损耗。为了减小芯片面积,我们采用折叠式的Lange耦合器。得到的MMIC移相器芯片面积仅为2.0×1.2 mm2。测试结果显示,在27GHz到32GHz的频率范围内,移相器的插入损耗为5.0 dB ± 0.8 dB,实现了360度连续移相,并且直流功率损耗为0。     

基于RSM和均匀试验的IC成品率设计方法

本文给出了一种基于均匀试验设计的响应表面模型，同时得到该模型在VLSI集成电路参数成品率中的优化方法。本方法首先对电路的关键参数进行扫描，确定满足电路基本性能时的参数变化范围。在此范围内，可对电路参数进行以数论方法为基础的均匀试验设计和建立响应表面。对拟合得到的响应表面模型进行CV拟合检验，求出最佳的电路设汁值。本方法适用于集成电路的工艺、器件和电路级的模拟。