量子效应对超薄沟道GeOI MOSFET电特性的影响

The impact of quantum confinement on the electrical characteristics of ultrathin-channel GeO1 n- MOSFETs is investigated on the basis of the density-gradient model in TCAD software. The effects of the channel thickness （Tch） and back-gate bias （Vbg） on the electrical characteristics of GeOI MOSFETs are examined, and the simulated results are compared with those using the conventional semi-classical model. It is shown that when T~h 〉 8 rim, the electron conduction path of the GeOI MOSFET is closer to the front-gate interface under the QC model than under the CL model, and vice versa when Tch 〈 8 rim. Thus the electrically controlled ability of the front gate of the devices is influenced by the quantum effect. In addition, the quantum-mechanical mechanism will enhance the drain-induced barrier lowering effect, increase the threshold voltage and decrease the on-state current; for a short channel length （≤ 30 nm）, when Tch 〉 8 nm （or 〈 8 nm）, the quantum-mechanical mechanism mainly impacts the subthreshold slope （or the threshold voltage）. Due to the quantum-size effect, the off-state current can be suppressed as the channel thickness decreases.     

Effect of Doping Profile on EPROM Programming

In EPROM devices, the gate injection current I_g is very sensitive to mobile electron density n and electric field E at the Si surface. We have investigated how n, E and I_g depend on doping profiles using a 2D electron temperature device simulator. We have studied a dual-gate EPROM device with channel length L=2(μm) and floating-gate oxide thickness T_(ox)=400 (?). The writing drain voltage of 17 volt results in a drain current of 1.2 mA. Equivalent floating-gate voltages (V_(gf)) of 12.8, 13.9 and 16 volts for three different channel profiles are found by adjusting the gate voltage on an equivalent MOSFET so that the drain current I_d is equal to this writing current.     

一种单材料双功函数栅MOSFET解析模型

An analytical surface potential model for the single material double work function gate(SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering(DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.     

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.     

Vertical-dual-source tunnel FETs with steeper subthreshold swing

In order to improve the drive current and subthreshold swing (SS), a novel vertical-dual-source tunneling field-effect transistor (VDSTFET) device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 μA at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 fA, an improved average subthreshold swing of 14 mV/dec, and a minimum point slope of 4 mV/dec.     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

Forward gated-diode method for parameter extraction of MOSFETs

The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs,especially when both of the variables are unknown previously.First,the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation (R-G) current are derived from the device physics.Then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction.The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method.     

槽栅MOSHEMT研制与特性分析

An A1GaN/GaN recessed-gate MOSHEMT was fabricated on a sapphire substrate. The device, which has a gate length of 1μm and a source-drain distance of 4μm, exhibits a maximum drain current density of 684mA/mrn at Vgs = 4V with an extrinsic transconductance of 219 mS/mm. This is 24.3% higher than the transconductance of conventional A1GaN/GaN HEMTs. The cut-off frequency and the maximum frequency of oscillation are 9.2 GHz and 14.1 GHz, respectively. Furthermore, the gate leakage current is two orders of magnitude lower than for the conventional Schottky contact device.     

Analytical modeling of subthreshold current and subthreshold swing of Gaussiandoped strained-Si-on-insulator MOSFETs

This paper presents the analytical modeling of subthreshold current and subthreshold swing of short- channel fully-depleted （FD） strained-Si-on-insulator （SSOI） MOSFETs having vertical Gaussian-like doping pro- file in the channel. The subthreshold current and subthreshold swing have been derived using the parabolic approx- imation method. In addition to the effect of strain on silicon layer, various other device parameters such as channel length （L）, gate-oxide thickness （tox）, strained-Si channel thickness （ts_Si）, peak doping concentration （Np）, project range （Rp） and straggle （op） of the Gaussian profile have been considered while predicting the device characteris- tics. The present work may help to overcome the degradation in subthreshold characteristics with strain engineering. These subthreshold current and swing models provide valuable information for strained-Si MOSFET design. Ac- curacy of the proposed models is verified using the commercially available ATLASTM, a two-dimensional （2D） device simulator from SILVACO.     

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.     

用于高压ESD保护的LDMOS中触发电压退化效应的研究

The trigger voltage walkin effect has been investigated by designing two different laterally diffused metal-oxide-semiconductor （LDMOS） transistors with an embedded silicon controlled rectifier （SCR）. By inserting a P＋ implant region along the outer and the inner boundary of the N＋ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5/zm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse （TLP） and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.     

CMOS反相器在高功率微波下闩锁效应的温度影响

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.     

Method of simulation of low dose rate for total dose effect in 0.18 μm CMOS technology

Three methods for simulating low dose rate irradiation are presented and experimentally verified by using 0.18 μm CMOS transistors.The results show that it is the best way to use a series of high dose rate irradiations, with 100 °C annealing steps in-between irradiation steps, to simulate a continuous low dose rate irradiation.This approach can reduce the low dose rate testing time by as much as a factor of 45 with respect to the actual 0.5 rad（Si）/s dose rate irradiation.The procedure also provides detailed information on the behavior of the test devices in a low dose rate environment.     

抗辐射加固版图技术的性能比较

Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.     

辐射对深亚微米NMOS器件热载流子效应的影响

We investigate how F exposure impacts the hot-carrier degradation in deep submicron NMOSFET with different technologies and device geometries for the first time. The results show that hot-carrier degradations on irradiated devices are greater than those without irradiation, especially for narrow channel device. The reason is attributed to charge traps in STI, which then induce different electric field and impact ionization rates during hotcarrier stress.     

12位CBCMOS工艺数模转换器电离辐射效应

A digital-to-analog converter （DAC） in CBCMOS technology was irradiated by 60Co F-rays at various dose rates and biases for investigating the ionizing radiation response of the DAC. The radiation responses show that the function curve and the key electrical parameters of the DAC in CBCMOS technology are sensitive to total dose and dose rates. Under different bias conditions, the radiation failure levels were different, and the radiation damage under operation bias conditions was more severe. Finally, test results were preliminarily analyzed by relating the failure mode to DAC architecture and process technology.     

Analysis of AIGaN/GaN high electron mobility transistors failure mechanism under semi-on DC stress

Semi-on DC stress experiments were conducted on A1GaN/GaN high electron mobility transistors （HEMTs） to find the degradation mechanisms during stress. A positive shift in threshold voltage （VT） and an increase in drain series resistance （RD） were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in Vx is the main factor leading to the degradation of saturation drain current （IDs）, while the increase in RD results in the initial degradation of Ios in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the A1GaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate-drain access region induced by the hot electron effect accounts for the increase in RD.     

Annealing before gate metal deposition related noise performance in AIGaN/GaN HEMTs

For a further improvement of the noise performance in A1GaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching： one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig-Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AIGaN/GaN HEMTs.     

浮结型碳化硅肖特基势垒功率二极管的优化设计

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics. Compared with the conventional power Schottky barrier diode, the device structure is featured by a highly doped drift region and embedded floating junction region, which can ensure high breakdown voltage while keeping lower specific on-state resistance, solved the contradiction between forward voltage drop and breakdown voltage. The simulation results show that with opti- mized structure parameter, the breakdown voltage can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.