塑封半导体器件的可靠性增长分析

应用ＥＤＲＩＣ可靠性模型对彩电配套用塑封整流二极管进行了增长分析,讨论了该器件的失效模式、失效机理及增长对策,使该器件的可靠性得到了较大的增长。     

维修性增长指标分配方案的决策与优选

对比了维修性增长分配与维修性分配的不同点,提出了维修性增长指标分配方案的决策与优选基本思路。应用最小二乘支持向量机(高斯径向核函数),建立了维修性影响因素与维修性特征量之间的映射关系,预测了增长方案的维修性指标MTTR和MPMT。通过分析影响维修性增长分配方案的投入和产出因素,构建了增长分配方案评价指标体系,并运用数据包络分析二次相对评价方法,对多种增长分配方案进行了排序。最后结合某型单相变流机维修性增长指标分配过程进行了实例分析。     

可靠性增长测定试验探讨

提出了可靠性增长测定试验的概念。探讨如何开展可靠性增长测定试验,使产品的可靠性得到确实的增长,响声生量值,当产品的可靠性达到了技术条件规定的要求时,可以免去可靠性鉴定试验。     

电子专用设备的可靠性试验

可靠性工程最基本的内容、最重要的工作项目就是可靠性试验。本文概述了可靠性试验的技术基础、可靠性试验的特点和分类，提供了电子专用设备可靠性试验的一些具体计划和方案。同时对可靠性试验数据的分析、处理方法作了一些简要的介绍。     

武器装备可靠性增长方法探讨

以空空导弹武器系统为例 ,在总结型号研制过程中开展可靠性管理、设计、试验的基础上 ,结合对部队保障、使用、维护情况的调查 ,对武器装备全寿命过程中实现可靠性增长的途径和方法进行了探讨。     

防空导弹可靠性增长试验加速方法的工程探索

结合防空导弹可靠性增长试验的工程实践,对加速试验方法在防空导弹弹上产品的可靠性增长试验中的应用进行了探索性的研究.提出在防空导弹可靠性增长试验中,对高可靠性要求的产品采用温度和振动联合加速应力来开展试验的工程方法.     

电子设备可靠性增长试验方法及应用研究

可靠性增长试验是对产品的可靠性进行调查、分析和评价的一种手段,对于可靠性要求高、产品子样少或价格昂贵的产品的可靠性增长和评价具有良好的实施效果。针对目前电子设备可靠性增长试验中的薄弱环节,对可靠性增长试验的关键技术进行了研究,阐述了电子设备如何制定可靠性增长试验的方案及程序,介绍了电子设备可靠性增长试验的制定原则和试验方法,并针对某型雷达可靠性增长试验给出设计和应用实例。     

电子产品研制阶段可靠性增长试验研究

结合工程实际经验,深入讨论了可靠性增长过程及实现途径,在保持试验条件和改进过程不变的条件下,实施了对具体型号电子产品的可靠性增长试验,达到了预期的可靠性增长目标,并且利用可靠性增长试验的数学模型(AMSAA模型)来评估产品的可靠性增长,对开展可靠性增长与可靠性增长试验工作具有重要的实际意义.     

电子产品研制阶段可靠性增长试验研究

在现代电子系统设备和可靠性增长工作的推动下,可靠性技术和工程实践得到了深入发展。结合工程实际经验,深入讨论了可靠性增长过程及实现途径。在保持试验条件和改进过程不变的条件下,实施了对具体型号电子产品的可靠性增长试验,达到了预期的可靠性增长目标,并且利用可靠性增长试验的数学模型(AMSAA模型)来评估产品的可靠性增长,对开展可靠性增长与可靠性增长试验工作具有重要的实际意义。     

Single-stage line-coupled ac/dc converter with high power factor and ripple-free input current

Single-stage line-coupled ac/dc converter with high power factor and ripple-free input current is proposed. The proposed power factor correction circuit can achieve high power factor and ripple-free input current using a coupled inductor. Experimental results for a 400?W converter at a constant switching frequency of 100?kHz are obtained to show the performance of the proposed converter.     

Modified current follower-based immittance function simulators

In this paper, four immittance function simulators consisting of a single modified current follower with single Z? terminal and a minimum number of passive components are proposed. The first proposed circuit can provide +L parallel with +R and the second proposed one can realise ?L parallel with ?R. The third proposed structure can provide +L series with +R and the fourth proposed one can realise ?L series with ?R. However, all the proposed immittance function simulators need a single resistive matching constraint. Parasitic impedance effects on all the proposed immittance function simulators are investigated. A second-order current-mode (CM) high-pass filter derived from the first proposed immittance function simulator is given as an application example. Also, a second-order CM low-pass filter derived from the third proposed immittance function simulator is given as an application example. A number of simulation results based on SPICE programme and an experimental test result are given to verify the theory.     

特种滤波器件对电磁干扰的抑制

由于电路的工作频率和周围环境中的电磁干扰频率越来越高,在产品实验过程中暴露的问题也日益增多。如何抑制电磁干扰问题?文中提供了以下三种滤波元件(馈通滤波器、滤波连接器、滤波阵列板)来帮助大家解决电磁干扰问题。     

Design techniques for high-speed multirate multistage FIR digital filters

This paper presents architecture design techniques for implementing both single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. A filter design example with TSMC 0.25?µm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714?MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.     

一种用于数字电视接收机的58dB IRR CMOS镜像抑制混频器

The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters（PPF） are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio（IRR） of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm.     

An Active Recursive RF Filter in 0.35 μm BiCMOS

An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is ?26 and ?34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.     

一种用于低电压集成锁相环的省面积的双通道环路滤波器

This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.     

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.     

一种适用于“模一”多带OFDM超宽带系统中跳频产生的3.96GHz锁相环

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.