一种低于1dB噪声系数的单片集成GNSS低噪声放大器

A monolithic integrated low noise amplifier(LNA) based on a SiGe HBT process for a global navigation satellite system(GNSS) is presented. An optimizing strategy of taking parasitic capacities at the input node into consideration is adopted and a method and design equations of monolithically designing the LC load and the output impedance matching circuit are introduced. The LNA simultaneously reaches excellent noise and input/output impedance matching. The measurement results show that the LNA gives an ultra-low noise figure of 0.97 dB, a power gain of 18.6 dB and a three-order input intermodulation point of..6 dBm at the frequency of 1.575 GHz. The chip consumes 5.4 mW from a 1.8 V source and occupies 600×650 μm2 die area.     

A 4–9 GHz 10W wideband power amplifier

A 4-9 GHz wideband high power amplifier is designed and fabricated, which has demonstrated saturated output power of 10 W covering 6-8 GHz band, and above 6 W over the other band. This PA module uses a balance configuration, and presents power gain of 7.3 ＋ 0.9 dB over the whole 4-9 GHz band and 39% power-added efficiency （PAE） at 8 GHz. Both the input and output VSWR are also excellent, which are bellow -10 dB.     

A Ku band internally matched high power GaN HEMT amplifier with over 30%of PAE

正We report a high power Ku band internally matched power amplifier(IMPA) with high power added efficiency(PAE) using 0.3μm AlGaN/GaN high electron mobility transistors(HEMTs) on 6H-SiC substrate.The internal matching circuit is designed to achieve high power output for the developed devices with a gate width of 4 mm.To improve the bandwidth of the amplifier,a T type pre-matching network is used at the input and output circuits,respectively.After optimization by a three-dimensional electromagnetic(3D-EM) simulator,the amplifier demonstrates a maximum output power of 42.5 dBm(17.8 W),PAE of 30%to 36.4%and linear gain of 7 to 9.3 dB over 13.8-14.3 GHz under a 10%duty cycle pulse condition when operated at V_(ds) = 30 V and V_(gs)=—4 V.At such a power level and PAE,the amplifier exhibits a power density of 4.45 W/mm.     

Design, fabrication and characterising of 100 W GaN HEMT for Ku-bandapplication

Ku-band GaN power transistor with output power over 100 W under the pulsed operation mode is presented. A high temperature AlN nucleation together with an Fe doped GaN buffer was introduced for the developed GaN HEMT. The AlGaN/GaN hetero-structure deposited on 3 inch SiC substrate exhibited a 2DEG hall mobility and density of ~2100 cm²/(V·s) and 1.0×10¹³ cm^-2, respectively, at room temperature. Dual field plates were introduced to the designed 0.25 μm GaN HEMT and the source connected field plate was optimized for minimizing the peak field plate near the drain side of the gate, while maintaining excellent power gain performance for Ku-band application. The load-pull measurement at 14 GHz showed a power density of 5.2 W/mm for the fabricated 400 μm gate periphery GaN HEMT operated at a drain bias of 28 V. A Ku-band internally matched GaN power transistor was developed with two 10.8 mm gate periphery GaN HEMT chips combined. The GaN power transistor exhibited an output power of 102 W at 13.3 GHz and 32 V operating voltage under pulsed operation mode with a pulse width of 100 μs and duty cycle of 10%. The associated power gain and power added efficiency were 9.2 dB and 48%, respectively. To the best of the authors'' knowledge, the PAE is the highest for Ku-band GaN power transistor with over 100 W output power.     

A NOVEL Ku-BAND LOW NOISE AMPLIFIER WITH HEMT AND GaAs MMIC

A novel Ku-band low noise amplifier with a high electron mobility transistor (HEMT)and a GaAs monolithic microwave integrated circuit (MMIC) has been demonstrated. Its noisefigure is less-than 1.9dB with an associated gain larger than 27dB and an input/output VSWRless than 1.4 in the frequency range of 11.7-12.2GHz. The HEMT and the microwave series in-ductance feedback technique are used in the first stage of the amplifier, and a Ku-band MMIC isemployed in the last stage. The key to this design is to achieve an optimum noise match and a min-imum input VSWR matching simultaneously by using the microwave series inductance feedbackmethod. The B J-120 waveguides are used in both input and output of the amplifier.     

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process

An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.     

Field plated 0.15μm GaN HEMTs for millimeter-wave application

SiN dielectrically-defined 0.15μm field plated GaN HEMTs for millimeter-wave application have been presented.The AlGaN/GaN hetero-structure epitaxial material for HEMTs fabrication was grown on a 3-inch SiC substrate with an Fe doped GaN buffer layer by metal-organic chemical deposition.Electron beam lithography was used to define both the gate footprint and the cap of the gate with an integrated field plate.Gate recessing was performed to control the threshold voltage of the devices.The fabricated GaN HEMTs exhibited a unit current gain cut-off frequency of 39 GHz and a maximum frequency of oscillation of 63 GHz.Load-pull measurements carried out at 35 GHz showed a power density of 4 W/mm with associated power gain and power added efficiency of 5.3 dB and 35%,respectively,for a 0.15 mm gate width device operated at a 24 V drain bias.The developed 0.15μm gate length GaN HEMT technology is suitable for Ka band applications and is ready for millimeter-wave power MMICs development.     

A digital input class-D audio amplifier with sixth-order PWM

A digital input class-D audio amplifier with a sixth-order pulse-width modulation(PWM)modulator is presented.This modulator moves the PWM generator into the closed sigma–delta modulator loop.The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma–delta modulator.Therefore,at the output of the modulator,a very clean PWM signal is acquired for driving the power stage of the class-D amplifier.A sixth-order modulator is designed to balance the performance and the system clock speed.Fabricated in standard 0.18 m CMOS technology,this class-D amplifier achieves 110 dB dynamic range,100 dB signal-to-noise rate,and 0.0056%total harmonic distortion plus noise.     

A Ka-band 22 dBm GaN amplifier MMIC

A Ka-band GaN amplifier MMIC has been designed in CPW technology,and fabricated with a domestic GaN epitaxial wafer and process.This is,to the best of our knowledge,the first demonstration of domestic Kaband GaN amplifier MMICs.The single stage CPW MMIC utilizes an AlGaN/GaN HEMT with a gate-length of 0.25μm and a gate-width of 2×75μm.Under V_ds=10 V,continuous-wave operating conditions,the amplifier has a 1.5 GHz operating bandwidth.It exhibits a linear gain of 6.3 dB,a maximum output power of 22 dBm and a peak PAE of 9.5%at 26.5 GHz.The output power density of the AlGaN/GaN HEMT in the MMIC reaches 1 W/mm at Ka-band under the condition of V_ds=10 V.     

一种应用于WiMAX协议的全集成3.5GHzCMOS功率驱动放大器

A fully integrated CMOS differential power amplifier driver(PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm~2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.     

CMOS反相器在高功率微波下闩锁效应的温度影响

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

A controllable resistor and its applications in pole-zero tracking frequency compensation methods for LDOs

This paper presents a controllable resistor, which is formed by a MOS-resistor working in the deep triangle region and an auxiliary circuit. The auxiliary circuit can generate the gate-source voltage which is proportional to the output current of an low dropout regulator for the MOS-resistor. Thus, the equivalent output resistance of the MOS-resistor is inversely proportional to the output current, which is a suitable feature for pole-zero tracking frequency compensation methods. By switching the type of the MOS-resistor and current direction through the auxiliary circuit, the controllable resistor can be suitable for different applications. Three pole-zero tracking frequency compensation methods based on a single Miller capacitor with hulling resistor, unit-gain compensation cell and pseudo-ESR （equivalent serial resistor of load capacitor） power stage have been realized by this controllable resistor. Their advantages and limitations are discussed and verified by simulation results.     

用于TFT-LCD驱动芯片的省面积高效率内置电荷泵

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump＇s power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.     

一种新颖的片内高压转低压电源转换方案

A novel power supply transform technique for high voltage IC based on the TSMC 0.6μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm^2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/℃. Compared with the traditional LDO （low dropout） regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.     

一种基于SOI基的N区控制阳极LIGBT新结构

A new lateral insulated-gate bipolar transistor （LIGBT） structure on SOI substrate, called an n-region controlled anode LIGBT （NCA-LIGBT）, is proposed and discussed. The n-region controlled anode concept results in fast switch speeds, efficient area usage and effective suppression NDR in forward I-V characteristics. Simulation results of the key parameters （n-region doping concentration, length, thickness and p-base doping concentration） show that the NCA-LIGBT has a good tradeoff between turn-off time and on-state voltage drop. The proposed LIGBT is a novel device for power ICs such as PDP scan driver ICs.     

A power scalable PLL frequency synthesizer for high-speed △-∑ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.     

一种应用于能量攫取系统的低功耗的工作于亚阈值区域的基准电压源的设计

We propose a bandgap reference, which works in sub-threshold regions to the reduce power consumption in applications such as those in energy harvesting systems that stimulate the development of power management for low power consumption applications.Measurements shows that the supply current of the proposed bandgap reference is only 6.87 μA, including a voltage buffer consuming 3.6 μA of supply current, when the supply voltage is 5 V.The supply voltage can vary from 3 to 11 V and the line regulation of the proposed bandgap reference output voltage is 0.875 mV/V at room temperature.The temperature coefficiency is 88.9 ppm from 10 to 100° C when the supply voltage is 5 V.     

A New Power Allocation Algorithm in Cognitive Radio Networks

Most resource allocation algorithms are based on interference power constraint in cognitive radio networks. Instead of using conventional primary user interference constraint, we give a new criterion called allowable signal to interference plus noise ratio （SINR） loss constraint in cognitive transmission to protect primary users. Considering power allocation problem for cognitive users over flat fading channels, in order to maximize throughput of cognitive users subject to the allowable SINR loss constraint and maximum transmit power for each cognitive user, we propose a new power allocation algorithm. The comparison of computer simulation between our proposed algorithm and the algorithm based on interference power constraint is provided to show that it gets more throughput and provides stability to cognitive radio networks.     

汽车电子零郜件EMC测试的供电问题

汽车电子零部件在进行EMC测试时，大家在关注不同的待测品（DUT）应该做什么项目的测试、需要用到什么样的测试仪器、试验时的具体布置及试验步骤前，首先要考虑如何给待测品（DUT）供电，使之能够正常工作。下文将介绍相关标准中提到的关于供电部分的要求及分析。