一种休眠机制下无线传感器网络的自治愈方法

为减少无线传感器网络(WSNs)大规模应用中出现的节点同步失效、数据丢失的问题,通过对现有WSNs应用系统的研究,提出了一种全网节点同步休眠机制下WSNs的自治愈方法.详细介绍了该方法的设计思路、实现方法及测试过程.测试结果表明:此方法可针对数据丢失和时间同步失效的节点进行节点自救,实现丢失节点的再入网、再同步,提高WSNs系统的稳定性,为WSNs的应用提供更好的条件.     

应用于高速CMOS图像传感器的10比特列并行循环式ADC

This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.     

基于分数频率合成器的多标准I/Q载波产生系统

本文基于sigma-delta分数频率合成器设计了多标准I/Q正交载波产生系统。通过合理的频率规划,此系统能够应用于多标准无线通讯系统。设计采用了0.13um的标准CMOS射频工艺。测试结果显示3个正交VCO的频率覆盖范围为3.1GHz至6.1GHz(65.2%),然后通过串联的除二分频器,可以使系统的频率连续覆盖0.75GHz至6GHz。整个芯片的面积是2.1mm1.8mm。在1.2V的电源电压下系统功耗为21.7mA(除去输出缓冲级)。利用频率预置技术,锁相环的锁定时间小于4us。并且在系统中加入了非易失性存储器(NVM),能够存储系统的一些数字配置信息包括锁相环的预置信息,利用NVM的非易失存储特性,使得整个系统能够避免重复的校正。     

基于短距离无线/有线通信的燃气监测报警系统

根据燃气泄漏多发区域对燃气浓度监测的需求,提出基于短距离无线/有线通信的燃气监测报警系统。系统选用通用的可燃气体传感器和温度传感器、8位单片机和433 MHz无线通信芯片为核心器件,完成无线/有线燃气监测报警终端的软硬件设计,设计完成了接收终端和上位机监控软件。燃气监测报警系统能对燃气浓度和环境温度远程实时地进行监测,具有动态显示、历史数据查询和二级报警等功能。     

一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路．BDD器件以电流模式的开关电流存储器为基本单元，具有符合二元判定图的两向通路的特点．用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路．给出了或门、异或门及四位加法器电路的例子，并使用HSPICE仿真器进行了仿真，验证了这种器件及其电路的正确性．     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

单电子数据转换电路

提出了两种新型的由单电子晶体管、MOS管和电容组成的数模转换(ADC)和模数转换(DAC)电路.这种混合ADC和DAC电路可在室温条件下工作且负载能力大,功耗低.对这种混合单电子晶体管和MOS管的ADC和DAC电路进行了仿真,仿真结果表明两种电路能够在室温条件下正常工作.采样频率达到100MHz以上,功耗约为0.1μW.     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

小面积低功耗RFID射频前端电路设计

提出了一个适用于EPC Gen2协议的小面积低功耗RFID射频前端电路的设计方案.射频前端电路包括整流器、ASK解调器、ASK和BPSK调制器和传感器模块,射频的工作频率为860～960 MHz.基于具有不挥发存储器和肖特基二极管选项的0.35μm CMOS工艺,设计了RFID射频前端电路.采用开关电容电路技术实现了小面积低功耗RFID射频前端电路.     

具有工艺补偿和毛刺消除功能的快速锁定频率预置锁相环频率综合器

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.