变温C-V和传输线模型测量研究AlGaN/GaN HEMT温度特性

通过对异质结材料上制作的肖特基结构变温C-V测量和传输线模型变温测量,研究了蓝宝石衬底AlGaN/GaN异质结高电子迁移率晶体管的直流特性在25～200℃之间的变化,分析了载流子浓度分布、沟道方块电阻、欧姆比接触电阻和缓冲层泄漏电流随温度的变化规律.得出了器件饱和电流随温度升高而下降主要由输运特性退化造成,沟道泄漏电流随温度的变化主要由栅泄漏电流引起的结论.同时,证明了GaN缓冲层漏电不是导致器件退化的主要原因.     

变温C-V和传输线模型测量研究AlGaN/GaN HEMT温度特性

通过对异质结材料上制作的肖特基结构变温C-V测量和传输线模型变温测量,研究了蓝宝石衬底AlGaN/GaN异质结高电子迁移率晶体管的直流特性在25～200℃之间的变化,分析了载流子浓度分布、沟道方块电阻、欧姆比接触电阻和缓冲层泄漏电流随温度的变化规律.得出了器件饱和电流随温度升高而下降主要由输运特性退化造成,沟道泄漏电流随温度的变化主要由栅泄漏电流引起的结论.同时,证明了GaN缓冲层漏电不是导致器件退化的主要原因.     

一种对称极化掺杂增强型高压GaN HFET

针对传统AlGaN/GaN HFET击穿电压远低于理论值,以及阈值电压与开态电流之间存在制约关系的问题,提出一种对称极化掺杂增强型高压GaN HFET。采用Al组分对称渐变的AlGaN势垒层,因极化梯度分别在正向渐变AlGaN层和逆向渐变AlGaN层中诱导产生了三维电子气(3DEG)和三维空穴气(3DHG)。利用3DHG,阻断了源极与3DEG之间的纵向导通沟道,实现了新的增强型模式。同时,正向渐变AlGaN层的高浓度3DEG显著提升了器件输出电流。器件关断时,极化电荷形成的极化结有助于耗尽漂移区,优化了电场分布,提升了器件耐压。与传统AlGaN/GaN HFET相比,新器件的击穿电压从39 V提高至919 V,饱和漏电流提升了103.5%。     

基于T型阳极场板下梯度掺杂的多通道AlGaN/GaN肖特基二极管的研究

为了降低微波无线能传输系统(MWPT)整流电路模块的能量损耗,使用AlGaN/GaN异质结肖特基二极管(SBD)可以有效地降低整流损耗。本文设计了一种高性能多通道SBD结构,其具有四个周期性重复AlGaN/GaN的异质结构。为了提高器件的反向特性,使用T型阳极和对不同的AlGaN势垒层采用不同掺杂浓度的方式。这种独特的多通道器件结构正向特性有了显著提升,导通电阻降低了74%,达到了2Ω·mm,导通电压降低了57%,达到了0.31 V。由于T型阳极和独特的Si掺杂方式,该结构的击穿电压达到了300 V。     

1400 V/240 mΩ增强型硅基p-GaN栅结构AlGaN/GaN HEMT器件

基于硅基p-GaN/AlGaN/GaN异质结材料结构,研制了一款横向结构的高压增强型GaN高电子迁移率晶体管(GaN HEMT)器件。通过采用自对准栅刻蚀与损伤修复技术以及低温无金欧姆合金工艺实现了较低的导通电阻,并借助于叠层介质钝化和多场板峰值抑制技术提升了器件的击穿特性。测试结果表明,所研制GaN器件的阈值电压为1.95 V(V_GS=V_DS,I_DS=0.01 mA/mm),导通电阻为240 mΩ(V_GS=6 V,V_DS=0.5 V),击穿电压高于1 400 V(V_GS=0 V,I_DS=1μA/mm),彰显了硅基p-GaN栅结构AlGaN/GaN HEMT器件在1 200 V等级高压应用领域的潜力。     

N极性GaN/AlGaN异质结和场效应晶体管（英文）北大核心CSCD

由于晶格的反转和随之而来的极化场的反转,N极性面氮化物材料已经成为微波功率器件应用的理想材料之一。在2英寸(1英寸=2.54cm)偏角度4H-SiC衬底上通过金属有机物化学气相沉积(MOCVD)的方法生长了N极性面GaN/AlGaN异质结材料,使用X射线衍射仪(HR-XRD)、原子力显微镜(AFM)、Raman光谱仪和扫描电子显微镜(SEM)等对材料进行了表征。结果表明,N极性面GaN/AlGaN异质结材料的二维电子气面密度和迁移率分别为0.92×1013cm^(-2)和1035cm^2/(V·s)。制备了N极性GaN/AlGaN异质结场效应晶体管(HFET)。测试结果表明,1μm栅长的n极性面GaN/AlGa NHFET器件峰值跨导为88.9mS/mm,峰值电流为128mA/mm。     

一种P-GaN栅极结合槽栅技术的增强型HEMT

为了得到高击穿电压、高阈值电压的增强型GaN器件,提出了一种P型掺杂GaN(P-GaN)栅极结合槽栅技术的AlGaN/GaN/AlGaN双异质结结构。该器件的阈值电压高达3.4 V,击穿电压达738 V。利用Sentaurus TCAD进行仿真,对比了传统P-GaN栅与P-GaN栅结合槽栅的AlGaN/GaN/AlGaN双异质器件的阈值电压和耐压。结果表明,栅槽深度在5~13 nm范围内变化时,阈值电压随栅槽深度的增大而增大,击穿电压随栅槽深度的增大呈先增大后略减小;导通电阻随槽栅深度的增大而增大,最小导通电阻为11.3 Ω·mm。     

基于MOCVD再生长n+ GaN 欧姆接触工艺fT/fmax＞150/210 GHz的AlGaN/GaN HFETs器件研究

基于SiC衬底AlGaN/GaN异质结材料研制具有高电流增益截止频率(fT)和最大振荡频率(fmax)的AlGaN/GaN异质结场效应晶体管(HFETs).基于MOCVD外延n+ GaN 欧姆接触工艺实现了器件尺寸的缩小, 有效源漏间距(Lsd)缩小至600 nm.此外, 采用自对准工艺制备了60 nm T型栅.由于器件尺寸的缩小, 在Vgs=2 V下, 器件最大饱和电流(Ids)达到2.0 A/mm, 该值为AlGaN/GaN HFETs器件直流测试下的最高值, 器件峰值跨导达到608 mS/mm.小信号测试表明, 器件fT和fmax最高值分别达到152 GHz和219 GHz.     

击穿电压提高的AlGaN/GaN/AlGaN双异质结特性

本文论述了AlGaN/GaN双异质结高电子迁移率晶体管的特性,该结构使用Al组分为7%的AlGaN来代替传统的GaN作为缓冲层。Al0.07Ga0.93N缓冲层增加了二维电子气沟道下方的背势垒高度,有效提高了载流子限阈性,从而造成缓冲层漏电的显著减小以及击穿电压的明显提高。对于栅尺寸为0.5100μm,栅漏间距为1μm的器件,AlGaN/GaN 双异质结器件的击穿电压（~100V）是常规单异质结器件的两倍（~50V）。本文中的双异质结器件在漏压为35V、频率为4GHz下,最大输出功率为7.78W/mm,最大功率附加效率为62.3%,线性增益为23dB。     

基于MOCVD再生长n_+ GaN欧姆接触工艺f_T/f_(max)>150/210 GHz的AlGaN/GaN HFETs器件研究（英文）

基于SiC衬底AlGaN/GaN异质结材料研制具有高电流增益截止频率(fT)和最大振荡频率(fmax)的AlGaN/GaN异质结场效应晶体管(HFETs).基于MOCVD外延n+GaN欧姆接触工艺实现了器件尺寸的缩小,有效源漏间距(Lsd)缩小至600 nm.此外,采用自对准工艺制备了60 nm T型栅.由于器件尺寸的缩小,在Vgs=2 V下,器件最大饱和电流(Ids)达到2.0 A/mm,该值为AlGaN/GaN HFETs器件直流测试下的最高值,器件峰值跨导达到608 mS/mm.小信号测试表明,器件fT和fmax最高值分别达到152 GHz和219 GHz.     

隔离型漏极扩展式NMOS器件能量耐受能力的提高

与衬底隔离的漏极扩展式NMOS器件被广泛应用于功率信号处理中。器件由于强电场引起的空穴电流会导致寄生NPN管导通,引起二次击穿,产生严重的可靠性问题。通过优化P型外延条件,埋层及N阱的杂质浓度分布,使得峰值电场降低百分之三十,空穴峰值电流降低百分之六十,大大抑制了寄生NPN效应。当Vgs=6V时,器件的I-V输出特性显示其开态击穿电压从28V提高到了37V,TLP测试结果显示能量耐受能力提高了百分之三十,同时器件的导通电阻等参数保持不变。     

Interface Modification to Improve Hole‐Injection Properties in Organic Electronic Devices

The performance of organic electronic devices is often limited by injection. In this paper, improvement of hole injection in organic electronic devices by conditioning of the interface between the hole‐conducting layer (buffer layer) and the active organic semiconductor layer is demonstrated. The conditioning is performed by spin‐coating poly(9,9‐dioctyl‐fluorene‐co‐N‐ (4‐butylphenyl)‐diphenylamine) (TFB) on top of the poly(3,4‐ethylene dioxythiophene): poly(styrene sulfonate) (PEDOT:PSS) buffer layer, followed by an organic solvent wash, which results in a TFB residue on the surface of the PEDOT:PSS. Changes in the hole‐injection energy barriers, bulk charge‐transport properties, and current–voltage characteristics observed in a representative PFO‐based (PFO: poly(9,9‐dioctylfluorene)) diode suggest that conditioning of PEDOT:PSS surface with TFB creates a stepped electronic profile that dramatically improves the hole‐injection properties of organic electronic devices.     

Measurement of hole leakage and impact ionization currents in bistable metal—tunnel-oxide—semiconductor junctions

The electron tunneling, oxide hole transport, and hot-electron impact ionization currents in bistable metal-tunnel-oxide-semiconductor (MTOS) junctions have been measured using a novel charge-coupled device charge packet insertion transient technique, and by steady-state hole injection. Good agreement was obtained between the two techniques. An electron-to-hole oxide current ratio in the range of 20-40 was observed for a 33-Å tunnel oxide. In addition, the impact ionization hole generation current was found to be 2-5 percent of the electron tunneling current. This excess hole generation appears to be balanced in the stable high current state by back diffusion from a super-inverted semiconductor surface. The impact ionization phenomenon results in a newly discovered voltage controlled n-type negative resistance when the MTOS junction is coupled to an adjacent p-n junction through the use of an intermediate control gate.     

用ZnS薄膜作为空穴缓冲层的高效率有机发光二极管

用磁控溅射方法制备的ZnS薄膜作为有机发光器件(OLEDs)的空穴缓冲层,使典型结构的 OLEDs(ITO/TPD/Alq/LiF/Al) 的发光性能得到改善.ZnS 缓冲层厚度对器件性能影响的实验结果表明,当ZnS缓冲层厚度为 5 nm 时,器件的亮度增加了2倍多;当ZnS缓冲层厚度为5、10 nm时,器件的发光电流效率增加40%.研究结果表明 ZnS 薄膜是一种好的缓冲层材料,它能够提高器件的发光效率,改善器件的稳定性.     

横向电阻区对IGBT过电流关断能力的影响研究

针对绝缘栅双极晶体管(IGBT)在过电流关断测试中被烧毁的问题,设计了三种不同的横向电阻区结构。为了分析器件的失效机理,研究不同结构横向电阻区对过电流关断能力的影响,借助Sentaurus TCAD仿真工具构建了器件模型,模拟了器件的整个过电流关断过程。对三种结构器件在过电流关断过程中的内部关键物理参量的变化情况进行分析,发现不同长度的横向电阻区对空穴的抽取效率不同,进而可以影响到电流密度分布。当电阻区增加到一定长度时,可以有效提升过电流关断能力,避免器件烧毁失效。     

以ZnO为空穴缓冲层的高效率有机电致发光器件

研制了在传统双层有机电致发光器件(OLED) ITO/NPB/AlQ/Al的阳极与空穴传输层间加入ZnO缓冲层的新型器件.研究了加入缓冲层后对OLED性能的影响,并比较了新型与传统OLED的性能,结果表明,新型器件比传统器件的耐压能力有了显著提高;当电压达到7 V时,发光效率提高了35%.分析认为,ZnO缓冲层的加入,改善了界面, 减少了漏电流,并且阻碍了空穴的注入,有利于改善空穴和电子的注入平衡,提高复合效率.     

Numerical analysis of the photoeffects in GaAs MESFET's

The photoeffects on the I-V characteristics of GaAs MESFETs have been studied by a two-dimensional numerical method. It is theoretically verified that the photovoltaic effect occurring at the channel/substrate interface is responsible for the substantial increase of the drain current. The reverse gate current due to illumination is caused by sweep-out by the high electrical field in the gate depletion region, where a large gradient in the depth profile of the hole Fermi energy is found. For devices with a lightly doped n-type buffer layer, the increase of the drain current is less than for devices without a buffer layer, but is still substantial     

High-resistivity sol-gel ITO thin film as an interfacial buffer layer for bulk heterojunction organic solar cells

Bulk heterojunction organic solar cells have been fabricated by inserting a high-resistivity sol-gel ITO buffer layer between an ITO anode and a PEDOT:PSS hole injection layer. The performance of the devices with the sol-gel ITO atop the ITO anodes treated by conventional annealing at 500 °C for 1 h and rapid thermal process (RTP) at 800 °C for 20 and 30 s was compared. The best power conversion efficiency of 3.5% was achieved for the device with the 15-nm-thick sol-gel ITO treated with RTP at 800 °C for 30 s, as compared with 2.7% of the standard device under an illumination of AM 1.5. In addition, the short circuit current of the device was significantly increased by 42.7%. The observed enhancement of the short circuit current can be attributed an interfacial energy step created by the high-resistivity sol-gel ITO between the ITO anode and the PEDOT:PSS.     

Low input resistance current buffer stage using a controllable positive feedback loop,and applications of current conveyor based filters

A novel current buffer stage with very low input resistance is proposed. Low input resistance is achieved using a potentially instable positive feedback loop. Stability of the circuit under different operating conditions is examined in details. A feedback control block using a bipolar 4-bit current steering DAC as a control mechanism is added to the buffer to control the input resistance and assure stability. The proposed technology-independent design methodology always ensures precision and stability for all different parasitic capacitor and resistor values of the driving signal source as well as for process, mismatch, and environmental variations. Additionally, a novel second generation current conveyor circuit based on this novel input buffer is presented to demonstrate how this buffer makes almost ideal current mode circuits possible. Filter applications using the proposed CCII are performed for further justification. The current buffer and CCII were built in AMS 0.35 μm 2P4M CMOS technology. Measurement results are presented for the current buffer, the CCII circuit, and the filters.     

Tensile-Strained Germanium CMOS Integration on Silicon

Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ~14 Aring) HfO₂ gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ~0.67% and exhibits a peak hole mobility of 250 cm²/V ldr s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.