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8W AlGaN/GaN HEMT功率器件的研制 总被引:2,自引:2,他引:0
报道了基于国产衬底以及国产外延的AlGaN/GaN HEMT X波段功率器件的研究进展.利用国产衬底以及外延材料,优化了器件栅场板的结构,研制成功栅长0.35μm,栅宽为lmm的微波功率器件.该器件输出电流密度达到0.83A/mm,击穿电压大于100V,跨导为236mS/mm,截止频率(fT)达到30GHz,最大振荡频率(fmax)为32GHz,8GHz下在片进行连续波测试,漏端电压为40V时测试得到功率增益4.9dB,输出功率达8W,功率附加效率(PAE)为45%. 相似文献
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报道了基于国产衬底以及国产外延的AlGaN/GaN HEMT X波段功率器件的研究进展.利用国产衬底以及外延材料,优化了器件栅场板的结构,研制成功栅长0.35μm,栅宽为lmm的微波功率器件.该器件输出电流密度达到0.83A/mm,击穿电压大于100V,跨导为236mS/mm,截止频率(fT)达到30GHz,最大振荡频率(fmax)为32GHz,8GHz下在片进行连续波测试,漏端电压为40V时测试得到功率增益4.9dB,输出功率达8W,功率附加效率(PAE)为45%. 相似文献
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研究了一种采用新的T型发射极技术的自对准InP/GaInAs单异质结双极晶体管.采用了U型发射极图形结构、选择性湿法腐蚀、LEU以及空气桥等技术,成功制作了U型发射极尺寸为2μm×12μm的器件.该器件的共射直流增益达到170,残余电压约为0.2V,膝点电压仅为0.5V,而击穿电压超过了2V.器件的截止频率达到85GHz,最大振荡频率为72GHz,这些特性使此类器件更适合于低压、低功耗及高频方面的应用. 相似文献
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InP DHBT 器件具有优异的高频特性、良好的散热、击穿和噪声性能,是实现超高频、低噪声功率放大
电路设计的最具性能优势的器件之一。文中简要介绍和分析了影响高频器件电性能参数的主要因素,优化了材料
结构和版图设计,最终采用三台面湿法化学腐蚀工艺、自终止工艺、自对准光刻工艺和空气桥工艺等加工工艺研制
得到发射极线宽0. 7 μm 的InP DHBT 器件,并配套集成了平行板电容和金属薄膜电阻,片内器件一致性良好。不断
缩小器件基区台面面积,器件电性能最终实现:最大直流增益β 为30,10 μA 下的集电极-发射极击穿电压BVCEO 为
3. 2 V,截止频率fT 为358 GHz,最大振荡频率fmax 为407 GHz。测试结果表明,该器件可应用于220 GHz 放大器、
100 GHz 以下压控振荡器等数模混合集成电路。 相似文献
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采用相同的欧姆接触,栅长为100 nm的T型栅以及50 nm的氮化硅(SiN)表面钝化等器件工艺,制备了漏源间距分别为2和3μm的AlGaN/GaN高电子迁移率场效应晶体管(HEMT).研究发现,当漏源间距从2μm增加至3μm后,器件的直流特性略有下降,如在Vgs为1V下的饱和电流密度从1.4 A/mm下降至1.3 A/mm.此外,器件的射频特性也略有下降,电流增益截止频率(fT)从121 GHz降至116 GHz,最大振荡频率(fmax)从201 GHz下降至189 GHz.然而,器件的击穿特性却有显著提升,击穿电压从44 V提升至87 V.在实际器件设计制备过程中可考虑适当增加漏源间距,在保持直流和射频特性的前提下,提升器件的击穿特性. 相似文献
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报道了利用B+注入实现AlGaN/GaN HEMT的有源层隔离。通过优化离子注入的能量和剂量,获得了1011Ω/□的隔离电阻,隔离的高阻特性在700°C下保持稳定。分别制作了用B+注入和台面实现隔离的AlGaN/GaN HEMT,测试表明B+注入隔离的器件击穿电压大于70V,相比于台面隔离器件40V的击穿电压有很大提高;B+注入隔离器件电流增益截止频率fT和最大振荡频率fmax分别达到15GHz和38GHz,相比台面隔离器件的12GHz和31GHz有一定程度提高。 相似文献
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基于蓝宝石衬底的高微波特性 Al Ga N/Ga N HEMTs功率器件 ,器件采用了新的欧姆接触和新型空气桥方案。测试表明 ,器件电流密度 0 .784A/mm,跨导 1 97m S/mm,关态击穿电压 >80 V,截止态漏电很小 ,栅宽 1 mm的器件的单位截止频率 ( f T)达到 2 0 GHz,最大振荡频率 ( fmax) 2 8GHz,2 GHz脉冲测试下 ,栅宽 0 .75 mm器件 ,功率增益1 1 .8d B,输出功率 3 1 .2 d Bm,功率密度 1 .75 W/mm。 相似文献
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提出了一种新型D-RESURF埋栅SOI LDMOS (EGDR-SOI LDMOS)结构,其栅电极位于P-body区的下面,可以在扩展的埋栅电极处形成多数载流子的积累层;同时,采用Double- RESURF技术,在漂移区中引入两区的P降场层,有效降低了器件的比导通电阻,并提高了器件的击穿电压.采用二维数值仿真软件MEDICI,对器件的扩展栅电极、降场层进行了优化设计.结果表明,相对于普通SOI LDMOS,该结构的比导通电阻下降了78%,击穿电压上升了22%. 相似文献
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To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm2 with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at Vgs=5 V and Vds=20 V is 16 mA with a gate width of 150 µm. 相似文献
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针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。 相似文献
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《Microelectronics Journal》2001,32(5-6):497-502
We proposed a new lateral double-diffused MOS (LDMOS) structure employing a double p/n epitaxial layer, which is formed on p− substrates. Trenched gate and drain are also employed to obtain uniform and high drift current density. The breakdown voltage and the specific on-resistance of the proposed LDMOS are numerically calculated by using a two-dimensional (2D) device simulator, Medici. The n− drift region and upper p− region of the proposed LDMOS are fully depleted in off-states employing the RESURF technique. The simulation results show that the breakdown voltage is 142 V and specific on-resistance is 183 mΩ mm2 when the cell pitch of the LDMOS is 7.5 μm. The proposed LDMOS shows better trade-off characteristics than the previous results. 相似文献
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A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures. 相似文献
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I. Corts P. Fernndez-Martínez D. Flores S. Hidalgo J. Rebollo 《Microelectronics Reliability》2008,48(2):173-180
The design and electrical performance of bulk silicon power LDMOS transistors for base station applications are analyzed in this paper. Power LDMOS transistors have been fabricated with a seven mask levels process technology including a LOCOS oxide in the drift region and a polysilicon field plate. Specific on-state resistances in the range of 3 mΩ × cm2 have been experimentally measured on fabricated LDMOS transistors with a voltage capability of 80 V and a threshold voltage around 2.5 V. Moreover, the impact of the basic geometrical and technological parameters on the voltage capability and on the on-state resistance is also analyzed. Special emphasis has been made on the existence of a premature breakdown by a punch-through mechanism due to the combination of a low Boron dose in the body region and an excessive phosphorous dose in the drift region. Technological solutions for avoiding this undesired phenomenon are also discussed. 相似文献
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提出了一种具有阶梯浅沟槽隔离结构的LDMOS.阶梯浅沟槽结构增加了漂移区的有效长度,改善了表面电场及电流的分布,从而提高了器件的击穿电压.借助器件模拟软件Silvaco对沟槽深度、栅长及掺杂浓度等工艺参数进行了优化设计.结果表明,在保证器件面积不变的条件下,新结构较单层浅沟槽隔离结构LDMOS击穿电压提升36%以上,而导通电阻降低14%. 相似文献