A physical-based pMOSFETs threshold voltage model including the STI stress effect

The physical threshold voltage model of pMOSFETs under shallow trench isolation(STI) stress has been developed.The model is verified by 130 nm technology layout dependent measurement data.The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET.The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11%improvement of average delay time.This indicates the importance of STI stress consideration in circuit design.     

Analysis of AIGaN/GaN high electron mobility transistors failure mechanism under semi-on DC stress

Semi-on DC stress experiments were conducted on A1GaN/GaN high electron mobility transistors （HEMTs） to find the degradation mechanisms during stress. A positive shift in threshold voltage （VT） and an increase in drain series resistance （RD） were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in Vx is the main factor leading to the degradation of saturation drain current （IDs）, while the increase in RD results in the initial degradation of Ios in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the A1GaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate-drain access region induced by the hot electron effect accounts for the increase in RD.     

深亚微米MOS晶体管匹配特性总剂量辐照效应研究

Based on 0.18 μm MOS transistors, for the first time, the total dose effects on the matching properties of deep submicron MOS transistors are studied. The experimental results show that the total dose radiation magnifies the mismatch among identically designed MOS transistors. In our experiments, as the radiation total dose rises to 200 krad, the threshold voltage and drain current mismatch percentages of NMOS transistors increase from 0.55% and 1.4% before radiation to 17.4% and 13.5% after radiation, respectively. PMOS transistors seem to be resistant to radiation damage. For all the range of radiation total dose, the threshold voltage and drain current mismatch percentages of PMOS transistors keep under 0.5% and 2.72%, respectively.     

陶瓷封装器件中浮空金属盖板的异常静电放电研究

The human body model(HBM) stress of a no-connect metal cover is tested to obtain the characteristics of abnormal electrostatic discharge,including current waveforms and peak current under varied stress voltage and device failure voltage.A new discharge model called the "sparkover-induced model" is proposed based on the results.Then,failure mechanism analysis and model simulation are performed to prove that the transient peak current caused by a sparkover of low arc impedance will result in the devices’ premature damage when the potential difference between the no-connect metal cover and the chip exceeds the threshold voltage of sparkover.     

Comparative study of leakage power in CNTFET over MOSFET device

A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported.The characteristics of both devices are observed as varying the oxide thickness.Thereafter,we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device.After simulation on the HSPICE tool,we observed that the high threshold voltage can be achieved at a low chiral vector pair.It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small.After that,we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices.We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect.It is observed that at below the 10 nm channel length,the threshold voltage is increased rapidly in the case of the CNTFET device,whereas in the case of the MOSFET device,the threshold voltage decreases drastically.     

GIDL应力下超薄栅氧LDD NMOS器件退化

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

A total dose radiation model for deep submicron PDSOI NMOS

In most of the total dose radiation models,the drift of the threshold voltage and the degradation of the carrier mobility were only studied when the bulk potential is zero.However,the measured data indicate that the total dose effect is closely related to the bulk potential.In order to model the influence of the bulk potential on the total dose effect,we proposed a macro model.The change of the threshold voltage,carrier mobility and leakage current with different bulk potentials were all modeled in this model,and the model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences,especially the part of the leakage current.     

雪崩PIN二极管中的电流丝运动

The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations.The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered.The voltage waveform varies periodically due to the motion of the filament.The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates.Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction,it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.     

Influence of the thickness change of the wave-guide layers on the threshold current of GaAs-based laser diode

The paper mainly deals with theoretical investigations of the effect of the thickness change of the waveguide layers on the threshold current. It is analyzed according to the result of a numerical simulation that asks how does the shift of the active region position affect the threshold current for a single quantum well (SQW) and double quantum well (DQW) laser diode (LD) with a relatively narrow waveguide. It is found that the variation trend of threshold current and optimum position of QW are different in SQW and DQW LD with 0.2 μm-thick waveguide, which may be due to the higher variation rate of optical loss in DQW LD with the shift of the active region. It is also found that in terms of either SQW or DQW LD, the variation tendency of the threshold current with a different loss coefficient of the p-cladding layer makes little difference for the relatively narrow waveguide LD. Moreover, the variation trend of the threshold current and the optimum position of QW is almost the same in SQW and DQW LD with 0.8 μm-thick waveguide, because the optical loss is small enough and the threshold current is dominated by the optical confinement factor (OCF) in QW.     

一种用于半桥功率IC的新型高压电平位移电路

In order to reduce the chip area and improve the reliability of HVICs,a new high-voltage level-shifting circuit with an integrated low-voltage power supply,two PMOS active resistors and a current mirror is proposed.The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit,but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on.The normally-on PMOS transistors do not,therefore,need to be fabricated in the depletion process.The current mirror ensures that the level-shifting circuit has a constant current,which can reduce the process error of the high-voltage devices of the circuit.Moreover,an improved RS trigger is also proposed to improve the reliability of the circuit.The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI,and the simulation results show that the function is achieved well.     

Anomalous junction leakage current induced by STI dislocations andits impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction     

Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics

Active-area layout dependence of MOSFET parametric characteristics and its reduction by reducing shallow trench isolation (STI)-induced mechanical stress were investigated. Threshold voltages (V/sub th/) and saturation drain currents (I/sub ds/) become sensitive to the active-area layout of MOSFET in scaled-down technology. This phenomenon is the effect of mechanical stress from STI edge, which reduces impurity diffusion in channel region and enhances carrier mobility. To reduce the STI-induced stress, we examined STI-wall-oxide nitridation and STI gap-fill-oxide densifying in pure N/sub 2/ ambient. These processes reduced the reoxidation of the STI wall oxide, therefore reduced the STI-induced stress. According to the new STI process, the active-area layout dependence of V/sub th/ and I/sub ds/ were reduced successfully.     

STI应力效应下的pMOSFET阈值电压物理模型

本文提出了浅沟道隔离（STI）应力效应下的P型MOSFET的阈值电压物理模型,并用不同STI版图位置的130纳米的器件数据进行了验证。基于此STI阈值电压模型,我们对比了p型MOSFET和n型MOSFET在STI应力下的阈值电压和迁移率的变化。数据表明,相比n型MOSFET,p型MOSFET的阈值电压更少地受到STI应力影响,但迁移率却更多地受到STI应力影响。基于此STI阈值电压模型,我们进行了九级震荡环电路的模拟。模拟数据显示,适当的STI应力能使电路平均延迟时间提高约11%,同时也说明了STI应力模型在电路设计中的重要性。     

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

In the present work, a high aspect ratio process (HARP) using a new O₃/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed     

Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs

On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.      

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.      

The use of convergent beam electron diffraction for stress measurements in shallow trench isolation structures

Shallow trench isolation (STI) is a promising technology for the isolation structures of the new generation of ULSI devices with dimensions below 0.18 μm. The various processing steps cause stress fields in STI structures, which can lead to defect formation in the silicon substrate. In their turn, stress fields affect the electrical parameters and the reliability of devices. Convergent beam electron diffraction (CBED) is used in this study to examine the influence of a wet and a dry pre-gate oxidation on the stress distribution around STI structures. The measurements are performed on STI structures with different width and spacing. CBED analysis is compared with bright-field TEM images. Defects are observed in high-strain areas of small isolated structures.     

通过优化额外的硼注入工艺减小STI对SONOS存储器的影响

The influence of shallow trench isolation (STI) on a 90 nm polysilicon–oxide–nitride–oxide–silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.     

Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance R/sub sd/. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed.