不同压力下螯合剂浓度在碱性Cu CMP中的影响

We propose the action mechanism of Cu chemical mechanical planarization(CMP) in an alkaline solution.Meanwhile,the effect of abrasive mass fraction on the copper removal rate and within wafer non-uniformity(WIWNU) have been researched.In addition,we have also investigated the synergistic effect between the applied pressure and the FA/O chelating agent on the copper removal rate and WIWNU in the CMP process.Based on the experimental results,we chose several concentrations of the FA/O chelating agent,which added in the slurry can obtain a relatively high removal rate and a low WIWNU after polishing,to investigate the planarization performance of the copper slurry under different applied pressure conditions.The results demonstrate that the copper removal rate can reach 6125 °/min when the abrasive concentration is 3 wt.%.From the planarization experimental results,we can see that the residual step height is 562 ° after excessive copper of the wafer surface is eliminated.It denotes that a good polishing result is acquired when the FA/O chelating agent concentration and applied pressure are fixed at 3 vol% and 1 psi,respectively.All the results set forth here are very valuable for the research and development of alkaline slurry.     

Investigation of aluminum gate CMP in a novel alkaline solution

Beyond 45 nm, due to the superior CMP performance requirements with the metal gate of aluminum in the advanced CMOS process, a novel alkaline slurry for an aluminum gate CMP with poly-amine alkali slurry is investigated. The aluminum gate CMP under alkaline conditions has two steps:stock polishing and fine polishing. A controllable removal rate, the uniformity of aluminum gate and low corrosion are the key challenges for the alkaline polishing slurry of the aluminum gate CMP. This work utilizes the complexation-soluble function of FA/O Ⅱ and the preference adsorption mechanism of FA/O Ⅰ nonionic surfactant to improve the uniformity of the surface chemistry function with the electrochemical corrosion research, such as OCP-TIME curves, Tafel curves and AC impedance. The result is that the stock polishing slurry (with SiO₂ abrasive) contains 1 wt.% H₂O₂ ,0.5 wt.% FA/O Ⅱ and 1.0 wt.% FA/O Ⅰ nonionic surfactant. For a fine polishing process, 1.5 wt.% H₂O₂ , 0.4 wt.% FA/O Ⅱ and 2.0 wt.% FA/O Ⅰ nonionic surfactant are added. The polishing experiments show that the removal rates are 3000±50 Å/min and 1600±60 Å/min, respectively. The surface roughnesses are 2.05±0.128 nm and 1.59±0.081 nm, respectively. A combination of the functions of FA/O Ⅱ and FA/O Ⅰ nonionic surfactant obtains a controllable removal rate and a better surface roughness in alkaline solution.     

Effect of copper slurry on polishing characteristics

The composition of the polishing solution is optimized by investigating the impact of the WIWNU (the so-called within-wafer-non-uniformity WIWNU) and the removal rate(RR) on the polishing characteristics of copper.The oxidizer concentration is 1 Vol%;the abrasive concentration is 0.8 Vol%;the chelating agent of the solution is 2 Vol%.The working pressure is 1 kPa.The defect on the surface is degraded and the surface is clean after polishing.The removal rate is 289 nm/min and the WIWNU is 0.065.The surface roughness measured by AFM after CMP(chemical mechanical planarization) is 0.22 nm.     

三种胍盐对低磨料浓度碱性阻挡层抛光液性能的影响

The influence of three kinds of guanidinium salt on the removal rate selectivity of different materials was studied during the barrier chemical mechanical polishing(CMP) process at first.The three kinds of guanidine saltguanidine hydrochloride,guanidine nitrate and guanidine carbonate.Then we compared the effect of the three kinds of guanidine salt on the dishing,erosion and surface roughness value.In the end,the reaction mechanism was studied through electrochemical analysis.All the results indicate that there is a better performance of the slurry with guanidine hydrochloride than the slurries with the other two kinds of guanidine salt.It effectively improved the removal rate selectivity and the surface roughness under the premise of low abrasive concentration and low polishing pressure,which is good for the optimization of the alkaline slurry for the barrier CMP process.     

新型碱性精抛液对300mm铜膜全局平坦化的影响

The copper removal rate and uniformity of two types copper slurries were investigated, which was performed on the 300 mm chemical mechanical planarization （CMP） platform. The experiment results illustrate that the removal rate of the two slurries is nearly the same. Slurry A is mainly composed ofa FA/OI1 type chelating agent and the uniformity reaches to 88.32%. While the uniformity of slurry B is 96.68%, which is mainly composed of a FA/OV type chelating agent. This phenomenon demonstrates that under the same process conditions, the uniformity of different slurries is vastly different. The CMP performance was evaluated in terms of the dishing and erosion values. In this paper, the relationship between the uniformity and the planarization was deeply analyzed, which is mainly based on the endpoint detection mechanism. The experiment results reveal that the slurry with good uniformity has low dishing and erosion. The slurry with bad uniformity, by contract, increases Cu dishing significantly and causes copper loss in the recessed region. Therefore, the following conclusions are drawn： slurry B can improve the wafer leveling efficiently and minimize the resistance and current density along the line, which is helpful to improve the device yield and product reliability. This investigation provides a guide to improve the uniformity and achieve the global and local planarization. It is very significant to meet the requirements for 22 nm technology nodes and control the dishing and erosion efficiently.     

多层铜布线CMP后表面残留CuO颗粒的去除研究

This article introduces the removal technology of CuO particles on the post CMP wafer surface of multi-layered copper. According to the Cu film corrosion curve with different concentrations of HEO2 and the effect curve of time on the growth rate of CuO film, CuO film with the thickness of 220 nm grown on Cu a surface was successfully prepared without the interference of CuC12.2H20. Using the static corrosion experiment the type of chelating agent （FA/O II type chelating agent） and the concentration range （10-100 ppm） for CuO removal was determined, and the Cu removal rate was close to zero. The effect of surfactant on the cleaning solution properties was studied, and results indicated that the surfactant has the effect of reducing the surface tension and viscosity of the cleaning solution, and making the cleaning agent more stable. The influence of different concentrations of FA/O I type surfactant and the mixing of FA/O II type chelating agent and FA/O I type surfactant on the CuO removal effect and the film surface state was analyzed. The experimental results indicated that when the concentration of FA/O I type surfactant was 50 ppm, CuO particles were quickly removed, and the surface state was obviously improved. The best removal effect of CuO on the copper wiring film surface was achieved with the cleaning agent ratio of FA/O II type chelating agent 75 ppm and FA/O I type surfactant 50 ppm. Finally, the organic residue on the copper pattern film after cleaning with that cleaning agent was detected, and the results showed that the cleaning used agent did not generate organic residues on the film surface, and effectively removes the organic residue on the water.     

Effect of alkaline slurry on the electric character of the pattern Cu wafer

For process integration considerations,we will investigate the impact of chemical mechanical polishing (CMP) on the electrical characteristics of the pattern Cu wafer.In this paper,we investigate the impacts of the CMP process with two kinds of slurry,one of which is acid slurry of SVTC and the other is FA/O alkaline slurry purchased from Tianjin Jingling Microelectronic Material Limited.Three aspects were investigated:resistance,capacitance and leakage current.The result shows that after polishing by the slurry of FA/O,the resistance is lower than the SVTC.After polishing by the acid slurry and FA/O alkaline slurry,the difference in capacitance is not very large. The values are 0.1 nF and 0.12 nF,respectively.The leakage current of the film polished by the slurry of FA/O is 0.01 nA,which is lower than the slurry of SVTC.The results show that the slurry of FA/O produced less dishing and oxide loss than the slurry of SVTC.     

The stability of a novel weakly alkaline slurry of copper interconnection CMP for GLSI

Chemical mechanical polishing (CMP) is one of the important machining procedures of multilayered copper interconnection for GLSI,meanwhile polishing slurry is a critical factor for realizing the high polishing performance such as high planarization efficiency,low surface roughness.The effect of slurry components such as abrasive (colloidal silica),complexing agent (glycine),inhibitor (BTA) and oxidizing agent (H2O2) on the stability of the novel weakly alkaline slurry of copper interconnection CMP for GLSI was investigated in this paper.First,the synergistic and competitive relationship of them in a peroxide-based weakly alkaline slurry during the copper CMP process was studied and the stability mechanism was put forward.Then 1 wt％ colloidal silica,2.5 wt％ glycine,200 ppm BTA,20 mL/L H2O2 had been selected as the appropriate concentration to prepare copper slurry,and using such slurry the copper blanket wafer was polished.From the variations of copper removal rate,root-mean square roughness (Sq) value with the setting time,it indicates that the working-life of the novel weakly alkaline slurry can reach more than 7 days,which satisfies the requirement of microelectronics further development.     

SiC单晶片化学机械抛光工艺参数模型的研究

Firstly, this paper presents an orthogonal test of six factors and five levels, called the chemical mechanical polishing （CMP） process parameters experiment, for determining the best process parameters and ranking the influencing factors from primary to secondary. The three most important factors are the polishing pressure, the polishing liquid concentration and the relative velocity ratio of polishing disk to polishing carrier. Then, based on this analysis, the three factors and three levels of the quadratic orthogonal regression test are put forward. A math- ematical model impacting the surface roughness has also been set up. Finally, this work has achieved a polished wafer, whose material removal rate （MRR） is in the range of 70-90 nm/h and the surface roughness （Ra） is between 0.3 nm and 0.5 nm.     

Mechanical and tribological properties of interlayer films for the damascene-Cu chemical-mechanical planarization process

Chemical-mechanical planarization (CMP) has emerged as the most preferred method to achieve excellent global and local planarity in the damascene-Cu process. As the feature sizes shrink, understanding the fundamentals of CMP is critical for successful implementation of the CMP process in sub 0.35-μm technology. It is also important to understand the effects of mechanical and tribological properties of the interlayer films on the CMP process to conduct successful evaluation and implementation of these materials. In this paper, we present the mechanical and tribological properties of various interlayer films (SiO₂, SiC, low-k B, low-k C, Ta, and Cu) and discuss the CMP process of the films in an alumina-based Cu slurry. Mechanical properties were evaluated using a nanoindentation technique. A micro-CMP tester was used to study the fundamental aspects of the CMP process. The coefficient of friction (COF) was measured during the process and was found to decrease both with downward pressure and with platen rotation. An acoustic sensor, attached to the substrate carrier, was used to monitor the process, and the signal was recorded to examine the difference in polishing behavior of these films. The acoustic emission (AE) signal was found to increase with the increase in platen velocity and pressure. Effects of machine parameters on the polishing behavior of the interlayer films and the correlation of mechanical properties with tribological properties have been discussed.     

一种应用于无线传感器网络的低电压低功耗上混频器

This paper presents an up-conversion mixer for 2.4-2.4835 GHz wireless sensor networks （WSN） in 0.18 μm RF CMOS technology. It was based on a double-balanced Gilbert cell type, with two Gilbert cells having quadrature modulation applied. Current-reuse and cross positive feedback techniques were applied in the mixer to boost conversion gain; the current source stage was removed from the mixer to improve linearity. Measured results exhibited that under a 1 V power supply, the conversion gain was 5 dB, the input referred 1 dB compression point was -11 dBm and the IIP3 was -0.75 dBm, while it only consumed 1.4 mW.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

90nm CMOS工艺低功耗20GHz比较器设计

A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.     

一种全集成高电源抑制比的低压差线性稳压器

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC （Shanghai, China）. Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO＇s active chip-area is only smaller than 0.02 mm2.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

High power single mode 980 nm AIGalnAs/AIGaAs quantum well lasers with a very low threshold current

To achieve low threshold current as well as high single mode output power, a graded index separate confinement heterostructure （GRIN-SCH） A1GaInAs/A1GaAs quantum well laser with an optimized ridge wave- guide was fabricated. The threshold current was reduced to 8 mA. An output power of 76 mW was achieved at 100 mA current at room temperature, with a slope efficiency of 0.83 W/A and a horizon divergent angle of 6.3°. The maximum single mode output power of the device reached as high as 450 mW.     

一种基于低中频接收相位选择发射结构的工作在2.4GHz面向WPAN应用的超低功耗收发机

This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.