一种新颖的D类音频功率放大器驱动电路

在D类功率放大器的设计中,为了提高驱动效率,需要一个高电平驱动H桥的高端LDNMOS管.文中设计了一种新颖的适用于D类功放的驱动电路,在芯片内部采用一个电荷泵电路.当芯片正常工作时,H桥低端LDNMOS管的驱动电平通过较大的电荷泵电容稳定在5.5V左右,H桥高端LDNMOS管的驱动电平通过自举电容高达18.8V,从而实现对D类功放H桥高端的驱动,这样既提高了驱动效率,又减少了对外部多个电源的需求.采用此电路的一款3-W的立体声D类功放已在TSMC06BCD工艺线投片,芯片效率高达89.67%,H桥高端和低端的导通电阻为320mΩ,电源抑制比(PSRR)为-62dB,THD低至0.1%,测量结果表明该驱动电路工作良好.     

一种新颖的D类音频功率放大器驱动电路

在D类功率放大器的设计中,为了提高驱动效率,需要一个高电平驱动H桥的高端LDNMOS管.文中设计了一种新颖的适用于D类功放的驱动电路,在芯片内部采用一个电荷泵电路.当芯片正常工作时,H桥低端LDNMOS管的驱动电平通过较大的电荷泵电容稳定在5.5V左右,H桥高端LDNMOS管的驱动电平通过自举电容高达18.8V,从而实现对D类功放H桥高端的驱动,这样既提高了驱动效率,又减少了对外部多个电源的需求.采用此电路的一款3-W的立体声D类功放已在TSMC06BCD工艺线投片,芯片效率高达89.67%,H桥高端和低端的导通电阻为320mΩ,电源抑制比(PSRR)为-62dB,THD低至0.1%,测量结果表明该驱动电路工作良好.     

采用高性能负压电荷泵的AMOLED驱动DC-DC转换器

提出了一种采用高性能负压电荷泵的有源矩阵有机发光二极管(AMOLED)驱动DC-DC转换器.正输出电压(VOP)由升压转换器(BOOST)和线性稳压器(LDO)级联产生,BOOST中使用前馈方法改善线性瞬态响应,LDO保证了芯片在全负载电流范围内输出电压的纹波.负输出电压(VON)由一种新颖负压电荷泵电路产生,电荷泵仅由MOSFET构成以提高效率.提出了一种新型的转换负压的电平转换电路,降低了开关管导通电阻并提高了负压效率.采用突发(BURST)控制模式提高了轻载效率.芯片采用0.18 μm BCD工艺,其VOP和VON分别为4.6V和-2.4 V,工作频率为1 MHz,正常工作时的负载电流为0～ 50 mA,最大电源效率为89.4％.VOP和VON的纹波均小于7 mV,线性瞬态响应均为5 mV,负载瞬态响应分别为5 mV和20 mV.负输出电压在-0.6～-2.4 V可调,调整步长为0.1V.     

一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

基于低压CMOS工艺的新型负电压型电荷泵电路

采用UMC 0.18 μm 1.8 V/3.3 V CMOS工艺设计并流片验证了一个应用于生医刺激器的新型负电压型电荷泵电路.介绍了几种典型的负电压型电荷泵电路,比较其优缺点,在此基础上设计了一个新型4级交叉耦合型负电压电荷泵.和现有的结构相比,该电路在启动过程和工作过程中都不存在过压问题,器件任意两端口之间的电压均小于电源电压VDD,同时降低了MOS器件衬底效应、反向漏电流对电荷泵效率的影响.电荷泵的电容采用MIM电容,升压电容为50 pF,输出电容为100 pF.芯片面积为2.3 mm×1.3 mm,测试结果表明负电压型电荷泵电路输出电压为-10.3 V,系统最高效率为56％.当输出电流为3.5 mA时,输出电容为100 pF时,纹波电压为150 mV.     

用于TFT-LCD液晶显示的可调电荷泵设计

为了满足TFT-LCD液晶显示的驱动要求,设计了一种通过控制饱和区MOS管的导通电阻来调节输出电压的可调电荷泵。与传统的电荷泵相比,该电荷泵通过负反馈系统进行控制,具有输出可调、最少外围器件、低纹波、易于集成等优点。采用此可调电荷泵电路的芯片已在UMC0.6μm-BCD工艺线投片,测试结果表明,该可调电荷泵电路工作良好,独特的稳压方式使得电荷泵输出纹波降至最低,并且电荷泵的电容尺寸小,从而减小了整个系统的PCB面积,可调电荷泵正电压输出范围为10～30V,负电压输出范围为-5～-30V,负载电流为50mA时,输出纹波为27mV,可调电荷泵的整体效率可达80%。     

一种用于TFT-LCD液晶显示的片内门宽调制控制器的设计

为了防止在液晶显示面板上发生闪烁和减小栅驱动器的馈通现象,设计了一种基于升压型DC-DC和电荷泵的用于TFT-LCD液品显示的片内门宽调制控制器.该控制器能减小液品显示功耗,减少栅走线和液晶面板之间的耦合效应,其输出延时可调并输入到栅驱动器中,从而避免液晶显示设备错误的显示.采用该门宽调制器的基于电流模PWM升压型DC-DC和电荷泵的芯片已在UMC 0.6μm BCD工艺线投片,DC-DC的效率高达93%,可调电荷泵输出电压为10～30V,测试结果证明该门宽调制控制器电路工作良好,其面积为0.3mm2,静态电流小于1μA.     

一种用于TFT-LCD液晶显示的片内门宽调制控制器的设计

为了防止在液晶显示面板上发生闪烁和减小栅驱动器的馈通现象,设计了一种基于升压型DC-DC和电荷泵的用于TFT-LCD液品显示的片内门宽调制控制器.该控制器能减小液品显示功耗,减少栅走线和液晶面板之间的耦合效应,其输出延时可调并输入到栅驱动器中,从而避免液晶显示设备错误的显示.采用该门宽调制器的基于电流模PWM升压型DC-DC和电荷泵的芯片已在UMC 0.6μm BCD工艺线投片,DC-DC的效率高达93%,可调电荷泵输出电压为10～30V,测试结果证明该门宽调制控制器电路工作良好,其面积为0.3mm2,静态电流小于1μA.     

一种面向Flash存算阵列的可调电荷泵北大核心

Flash存算阵列在工作模式下需要用到不同内部驱动电压，因此基于当前各类Dickson型电荷泵，设计了一种针对Flash存算阵列的可调电荷泵。采用一种新型输出级的交叉耦合设计，解决了传统电荷泵最后一级阈值电压导致的低泵送效率的问题，并通过辅助MOS管增强了传统电荷泵中体源二极管对反向漏电流的抑制能力。55 nm CMOS工艺下的仿真结果表明，与改进前的电荷泵相比，在电源电压1.8 V和300μA的工作电流下，中间级反向漏电流减少了17.5%,输出级反向漏电流减少了73.1%。无反馈调节时，主电荷泵最高输出电压为9.56 V,电压效率达88.51%。PFM可调制模式下，可重构电荷泵能实现输出电压切换。     

用于相变存储器的超低输出纹波2X/1.5X电荷泵

本文针对相变存储器编程驱动电路,提出了一种超低输出电压纹波的开关电容型电荷泵。该电荷泵可根据输入电压的不同,自适应工作在2X/1.5X升压模式之间,以获得更高的电源转换效率。相比于传统开关电容型电荷泵,在充电阶段泵电容被充电至预先设定的电压值Vo-VDD(Vo为预期的输出电压);放电阶段,泵电容串联在输入电压VDD与输出端,通过此方法将电荷泵输出端电压稳定在Vo,并有效的降低了由于电荷分享所造成的输出纹波。在中芯国际40nm标准CMOS工艺模型下,对电路进行了仿真验证,结果表明在输入电压为1.6-2.1V,输出2.5V电压,最大负载电流为10mA,输出电压纹波低于4mV,电源效率最高可达91%。     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.     

双模式高集成负电荷泵电路设计

提出了一种新颖的双模式高集成开关电容电荷泵。该电荷泵集成高频振荡器、电平移位、逻辑驱动以及4个功率MOSFET开关。与传统电荷泵相比,该电路可以工作在单电源以及双电源两种模式。单电源模式下,输出电压为-VCC;双电源模式下,输出电压为-3×VCC。电路采用0.35μm BCD工艺实现。测试结果表明:室温时,单电源模式和双电源模式下电荷泵输出电流分别为36 mA和80 mA时输出电压分别为-3.07 V和-12.10 V。在-55℃到125℃温度范围内,单电源模式和双电源模式下电荷泵输出电流分别为24 mA和50 mA时输出电压分别低于-3.06 V和-12.35 V。该电荷泵在两种模式下工作特性良好,已应用于相关工程项目。     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

新型浮栅MOS单管动态比较器设计

提出一种新型浮栅MOS单管动态比较器的电路结构。以浮栅MOS单管为核心,根据浮栅电荷的保持特性,在时钟控制下,两个电压分时地输入浮栅MOS管从而引起浮栅电位变化,相对变化后的浮栅电位决定着比较管的再通断,使预充电的输出电容与源极电容重新分配电荷,通过输出电容上电压是否发生变化来反映比较结果。单管比较避免差分对管由于工艺偏差所引起的输入失调问题,而且以浮栅偏置抵消MOS管的阈值。采用charted0.35μmCMOS工艺设计电路,面积约为0.003mm2,经前、后仿真和流片测试,结果表明,电路功能正确。并且在3.3V电源电压下、比较时间为0.4μs时,平均功耗为2.8mW。     

一种高增益低功耗CMOS LNA设计

采用TSMC0.18μmCMOS工艺,利用ADS2008软件仿真,设计了一种高增益的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在晶体管M3的栅源极处并入电容C1,以增加系统抗干扰能力;并在级间引入一并联电感和电容与寄生电容谐振,以提高增益。仿真结果表明,在2.4 GHz工作频率下,该电路的增益大于20 dB,噪声系数小于1 dB,工作电压为1.5 V,功耗小于5 mW,且输入输出阻抗匹配良好。     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

A self-boost charge pump topology for a gate drive high-side power supply

A self-boost charge pump topology is presented for a floating high-side gate drive power supply that features high voltage and current capabilities for use in integrated power electronic modules (IPEMs). The transformerless topology uses a small capacitor to transfer energy to the high-side switch from a single power supply referred to the negative rail. Unlike conventional bootstrap power supplies, no switching of the main phase-leg switches is required to provide power continuously to the high-side gate drive, even if the high-side switch is permanently on. Additional advantages include low parts-count and simple control requirements. A piecewise linear model of the self-boost charge pump is derived and the circuit's operating characteristics are analyzed. Simulation and experimental results are provided to verify the desired operation of the new charge pump circuit. Guidelines are provided to assist with circuit component selection in new applications.