原子钟噪声的多尺度分形特征

将小波分析理论和分形理论结合起来，讨论原子钟噪声的多尺度分形特征。文中研究结果表明，在大尺度上，原子钟噪声具有某种以周期变化；在小尺度上，原子钟噪声是完全随机的变化特征。     

新息滤波交互多式模型噪声辨识算法

预先或在线获取系统噪声的统计特性，往往是有效设计一个估计器或控制器的先决条件，早期关于噪声辨识的工作主要针对平稳或统计特性缓变的噪声过程，本文提出了一种混合系统噪声辨识新算法，该算法将新息滤波与交互式多模型算法结合起来，前者降低了权概率系数对量测噪声的敏感程度，而后者则是基于混合系统模态的马尔可夫链过程实现多模型的动态交互与动态切换，仿真结果证明了本文新算法有效性。     

新息滤波交互式多模型噪声辨识算法

预先或在线获取系统噪声的统计特性，往往是有效设计一个估计器或控制器的先决条件．早期关于噪声辨识的工作主要针对平稳或统计特性缓变的噪声过程．本文提出一种混合系统噪声辨识新算法，该算法将新息滤波与交互式多模型算法结合起来，前者降低了权概率系数对量测噪声的敏感程度，而后者则是基于混合系统模态的马尔可夫链过程实现多模型的动态交互与动态切换．仿真结果证明了本文新算法的有效性．     

单脉冲导引头对多干扰源的角分辨

当多个噪声调频干扰同时进入单脉信号引头主波束内时，导引头对干扰源的角度分辨是非常困难的。本文主要研究了导引头单脉冲接收机对宽带噪声调频干扰源的响应，分析了当单脉冲主波束内存在多个噪声调频干扰源时，导引头指向角的跟踪规律，并重点讨论了一种用聚类来提取角信息的方法，最后仿真证实了该方法的正确性和有效性。     

一种中大功率多路低噪声开关电源的设计

高精密电子系统对开关电源的低噪声要求日趋普遍,需求功率也日益增大。针对开关电源的噪声来源与特点,综合利用多重噪声抑制措施方有可能实现低输出噪声。着重介绍了一种多路输出开关电源的低噪声设计思路,从基础变换电路的低噪声设计和外围电路的低噪声处理方面进行了分析,对开关管、整流管、变压器辐射、布局布线与引出线处理、共模噪声抑制等采取对应噪声抑制方法。最后运用该方案试制了一款实际电路,通过实测表明设计满足预期要求。     

1/f分形噪声的一种多尺度Kalman滤波方法

针对淹没在1／f分形噪声中的有用信号恢复问题，提出了一种基于小波变换与Kalman滤波的多尺度滤波算法。首先将带有1／f分形噪声的信号分解成多尺度的子带信号，通过小波变换对1／f分形噪声的白化作用，消除了1／f分形噪声的自相似性和长程相关性。然后在小波域内，利用Kalman滤波实现了噪声和有用信号的分离，估计出了各子带中的有用信号。最后进行小波重构，较好地恢复出淹没在1／f分形噪声中的有用信号。仿真实验表明，使用多尺度Kalman滤波器能有效地抑制分形噪声，显著地提高了信噪比。     

一种用于雷达多目标角度超分辨的新方法

在现代脉冲雷达中，加性噪声不一定是高斯噪声，如果利用二阶统计量进行估计，将会带来较大误差，从阵列信号处理的角度出发，采用基于子空间的Root-MUSIC算法，提出了一种新估计量以分辨多个独立目标。通过对等幅调相信号的仿真，验证了该新估计量有较好的性能。     

极低本底单频激光相对强度噪声测试方法研究

针对高速光通信和微波光子系统对单频激光源极低相对强度噪声（RIN）的需求，开展了极低本底相对强度噪声测试方法的研究。首先分析了相对强度噪声测试中激光相对强度噪声、系统散粒噪声和热噪声等主要要素的影响，然后提出了基于增大光电流并结合低热噪声的频谱探测的方式降低测量极限的方法，实现了极低本底单频激光相对强度噪声测试，频谱分析频段可达到40 GHz，测量本底达-171 dBc/Hz。基于该方法和系统，更加精细地研究、表征了光通信中的光放大和强度调制过程的相对强度噪声特征，清晰地展示了极低本底下典型激光光源的噪声滚降和多个弛豫振荡峰、强度调制谐波失真等特性，证实了极低本底噪声测量方法的有效性。研究结果在激光器性能的设计优化和应用系统的选型评估等方面具有重要的应用前景。     

一种用于抑制椒盐噪声的多窗口中值滤波器

该文提出了一种用于抑制椒盐噪声的多窗口中值滤波算法。算法在招待过程中根据具体情况采用不同大小的滤波窗口。仿真结果表明，与标准中值滤波算法相比，该方法不仅可以有效去除图像中的椒盐噪声，特别是在噪声密度非常大的情况下，表现了很好的性。     

低位量化对数字化多频连续波雷达测距性能的影响

对基于FFT数字比相技术的多频连续波雷达，量化特别是低位量化必然对雷达的测距精度具有一定的影响。首先给出了极小化量化处理的实现方法，然后比较了极小化量化与均匀量化在同等条件下的量化噪声的方差及信噪比损失，推导出考虑量化噪声时多频连续波雷达测距误差均方根的计算公式，最后通过仿真结果验证了低位量化噪声对测距精度的影响，尤其是1位或2位量化对测距精度的影响。     

A Fast Macro-Model for Substrate Coupling and Ground Bounce Induced Substrate Noise Simulation in Mixed Signal VLSI

This paper discusses a novel substrate modeling technique for the simulation of substrate noise in mixed signal VLSI systems. This model yields to easy merger with the SPICE simulation netlist for the complete pre and post layout estimation of substrate noise effects in large mixed signal VLSI chips. Compared to previous numerous efforts in substrate noise modeling ranging from finite element methods (FEM) to boundary elements methods (BEM), this model, based on a finite sheet resistor slicing scheme also incorporates the effect of supply rail bounce due to bonding wire inductances, and, provides realistic estimates of substrate noise effects with a high degree of computational efficiency. Substrate noise simulations were done using a 0.18 m TSMC CMOS process technology using typical process parameters. A differential switched capacitor sample and hold circuit and a linear differential transconductor stage was used for the performance evaluation of this novel substrate model. Simulation results indicate a typical increase in Total Harmonic Distortion (THD) by atleast 6 dB due to the substrate noise effects, which corresponds to a performance loss by around 1-b precision. Also, the substrate noise effects are found to be proportional to the oversampling ratio (i.e., the digital clocking rate with respect to the input signal) and the net number of logic transitions at each register transfer instance in the mixed signal chip.     

Impact of low-frequency substrate disturbances on a 4.5 GHz VCO

This paper presents the impact of low-frequency substrate disturbances on a fully integrated voltage-controlled oscillator (VCO) spectrum. A 4.5 GHz VCO test-chip is presented; two substrate taps are placed inside the VCO core to measure or to inject disturbances into the substrate. The VCO carrier frequency sensitivity function of the tuning voltage and the bias current are measured. Then, the VCO spurious side-bands caused by harmonic substrate noise disturbances are analyzed to find a relation between the substrate noise characteristics and spur magnitudes. Theoretically the impulse sensitivity function (ISF) approach is used to analyze device sensitivity to substrate noise. Finally, a significant link between device sensitivity functions, low-frequency substrate disturbances and the VCO side-band spectral power, is demonstrated. According to this study, we conclude that a global approach which only considers power supply bounces in mixed IC's is not sufficient to analyze the sensitivity of RF integrated oscillators to low frequency substrate noise.     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

A physical-based noise macromodel for fast simulation of switching noise generation

Efficient prediction of the substrate noise generated by large digital sections is currently a major challenge in System-on-a-Chip design. A macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel is generated from identification of the physical elements relevant to noise generation. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are proposed. Using this macromodel, prediction of the noise generated by large digital sections can be easily done following a methodology based on high-level logic simulation. As a first step to validation, the macromodel accuracy is demonstrated in some circuits consisting of a reduced number of gates.     

混合信号衬底耦合噪声的传播及抑制方法

介绍了衬底噪声耦合效应在不同工艺衬底中的传播,应用medici模拟了不同衬底中,噪声发生端和噪声接收端噪声在不同间距下噪声传播的情况,并从工艺和电路设计两个方面介绍了一系列抑制衬底噪声的方法。     

一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

Assessment of carbon nanotube array transistors: A three-dimensional quantum simulation

The noise characteristics of advanced silicon semiconductor devices fabricated with FinFET technology are investigated and modeled at the probe tip reference planes in the microwave frequency range. The transistor noise model is obtained by assigning an equivalent temperature to each resistor of the small signal equivalent circuit. These temperatures are selected to be equal to the room temperature with the exception of the temperature values of the intrinsic output, feedback, and substrate resistances, which are selected in order to reproduce accurately the 50 Ω noise factor measurements over a broadband frequency range going from 0.5 GHz up to 26.5 GHz. Accurate model simulations are obtained at such high frequencies, thanks to the inclusion of the noise temperature associated to the feedback and substrate resistances representing non-quasi-static effects which cannot be neglected in the investigated frequency range.     

基于自适应滤波的噪声抵消法

语音降噪就是从带噪语音信号中提取尽可能纯净的原始语音。文中介绍了一种基于自适应滤波的噪声抵消法，采用归一化最小均方误差算法，采集实际噪声环境下各种不同信噪比的带噪语音样本进行降噪处理，实验结果表明，处理后信号的信噪比得到了较大程度的提高，大大改善了听音效果，具有很高的可懂度，且语音自然度好，没有失真；并与谱减法进行了比较，自适应噪声抵消法的降噪幅度比谱减法有一定提高，在听音效果上，用自适应噪声抵消法处理后的语音在清晰度、自然度方面优于谱减法。     

低噪声、低功耗CMOS电荷泵锁相环设计

设计了一种 1 .8V、0 .1 8μm工艺的低噪声低功耗锁相环电路 ,其采用 CSA(Current Steer Amplifier)架构的压控振荡器 (VCO)。整个电路功耗低 ,芯片面积为 1 60 μm× 1 2 0 μm,对电源和衬底噪声抑制能力强。经过Spice模拟表明 ,在有电源噪声的情况下 ,输出 5 0 0 MHz时钟时周对周抖动小于 41 ps,功耗为 2 .8m W,最终与芯片的量测结果基本一致