针对电容型MEMS读出电路噪声与失调的优化

This paper presents a high precision CMOS readout circuit for a capacitive MEMS gyroscope. A continuous time topology is employed as well as the chopper noise cancelling technique. A detailed analysis of the noise and mismatch of the capacitive readout circuit is given. The analysis and measurement results have shown that thermal noise dominates in the proposed circuit, and several approaches should be used for both noise and mismatch optimization. The circuit chip operates under a single 5 V supply, and has a measured capacitance resolution of 0.2 aF/√Hz. With such a readout circuit, the gyroscope can accurately measure the angular rate with a sensitivity of 15.3 mV/°/s.     

Design of a low noise distributed amplifier with adjustable gain control in 0.15μm GaAs PHEMT

正A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor(PHEMT) technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point(IIP3),which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm~2.     

A 0.18μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.     

A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...     

A △∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator（QVCO） is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz（17.5%）.Measured tuning gain of the QVCO(K_vco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm².     

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

一种集成二进制权精确对数线性可编程增益放大器的卫星导航接收机数字自动增益控制环路

A novel digitally controlled automatic gain control(AGC) loop circuitry for the global navigation satellite system(GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier(PGA),an AGC circuit and an analog-to-digital converter(ADC), which is implemented in a 0.18 m complementary metal–oxide–semiconductor(CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide d B-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than165 s while consuming an average current of 1.92 mA at 1.8 V.     

一种基于倾斜悬臂梁的高性能硅微陀螺

This paper presents a novel structure for improving the stability and the mechanical noise of micromachined gyroscopes. Only one slanted cantilever is used for suspension in this gyroscope, so the asymmetry spring and the thermal stress, which most micromachined gyroscopes suffer from, are reduced. In order to reduce the mechanical noise, the proof masses are designed to be much larger than in most micromachined gyroscopes. The gyroscope chip is sealed at 0.001 Pa vacuum. A gyroscope sample and its read-out circuit are fabricated. The scale factor of this gyroscope is measured as 57.6 mV/（deg/sec） with a nonlinearity better than 0.12% in a measurement range of ±100 deg/sec. The short-term bias stability in 20 min is 60 deg/h.     

应用于K波段使用了一种新的可变电感的20~25.5G的压控振荡器

A novel transformer-type variable inductor is proposed to achieve a wide tuning range at frequencies as high as K band. The variable inductor is designed, and an intuitive model is built to analyze its performance by HFSS. A lot of mathematical analysis is done in detail. A VCO using the proposed variable inductor is designed with TSMC 0.13 μm CMOS technology for verification. The frequency tuning range of the VCO depends on the proposed variable inductor. The phase noise of the VCO depends on the quality of the LC tank （including the proposed variable inductor and varactors）. So a specific AMOS varactor is implemented to improve its quality factor. The VCO is simulated at three typical TSMC fabrication comers （TT, FF, SS） to predict its measure results. The post simulation results shows that the VCO achieves a 20-25.5 GHz continuous tuning range. Its phase noise results at 1 MHz offset are -108.4 dBc/Hz and -100.5 dBc/Hz respectively at the tuning frequencies of 19.6 GHz and 25.5 GHz. The VCO draws only 3 to 6 mA from a 1.2 V power supply.     

12位CBCMOS工艺数模转换器电离辐射效应

A digital-to-analog converter （DAC） in CBCMOS technology was irradiated by 60Co F-rays at various dose rates and biases for investigating the ionizing radiation response of the DAC. The radiation responses show that the function curve and the key electrical parameters of the DAC in CBCMOS technology are sensitive to total dose and dose rates. Under different bias conditions, the radiation failure levels were different, and the radiation damage under operation bias conditions was more severe. Finally, test results were preliminarily analyzed by relating the failure mode to DAC architecture and process technology.     

Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes.     

W波段增益为25.7 dB两级cascode放大器

AW-bandtwo-stageamplifierMMIChasbeendevelopedusingafullypassivated 2 × 20 μm gate-width and 0.15 μm gate-length InP-based high electron mobility transistor （HEMT） technology. The two-stage amplifier has been realized in combination with a coplanar waveguide technique and cascode topology, thus leading to a compact chip-size of 1.85 × 0.932 mm^2 and an excellent small-signal gain of 25.7 dB at 106 GHz. Additionally, an inter-digital coupling capacitor blocks low-frequency signal, thereby enhancing the stability of the amplifier. The successful design of the two-stage amplifier MMIC indicates that InP HEMT technology has a great potential for W-band applications.     

大功率平面连接结构倒装LED的热仿真及热分析

Conventional GaN-based flip-chip light-emitting diodes （CFC-LEDs） use Au bumps to contact the LED chip and Si submount, however the contact area is constrained by the number of Au bumps, limiting the heat dissipation performance. This paper presents a flat surface high power GaN-based flip-chip light emitting diode （SFC-LED）, which can greatly improve the heat dissipation performance of the device. In order to understand the thermal performance of the SFC-LED thoroughly, a 3-D finite element model （FEM） is developed, and ANSYS is used to simulate the thermal performance. The temperature distributions of the SFC-LED and the CFC-LED are shown in this article, and the junction temperature simulation values of the SFC-LED and the CFC-LED are 112.80 ℃ and 122.97℃C, respectively. Simulation results prove that the junction temperature of the new structure is 10.17 ℃ lower than that of the conventional structure. Even if the CFC-LED has 24 Au bumps, the thermal resistance of the new structure is still far less than that of the conventional structure. The SFC-LED has a better thermal property.     

97dB动态范围、带温度补偿的MEMS电容传感器读出电路

This paper presents a charge-sensitive-amplifier(CSA)based readout circuit for capacitive microelectro-mechanical-system(MEMS)sensors.A continuous-time(CT)readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits.An operational trans-conductance amplifier(OTA)structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal.An analog temperature compensation method is proposed,which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity.The chip is designed and implemented in a 0.35 m CMOS process and is 2.1 2.1 mm2in area.The measurement shows that the readout circuitachieves0.9aF/√Hz capacitive resolution,97dBd ynamic range in 100Hz signal bandwidth,and 0.8mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

圆片级低温富锡金锡键合

Sn-rich Au–Sn solder bonding has been systematically investigated for low cost and low temperature wafer-level packaging of high-end MEMS devices.The AuSn2 phase with the highest Vickers-hardness among the four stable intermetallic compounds of the Au–Sn system makes a major contribution to the high bonding shear strength.The maximum shear strength of 64 MPa and a leak rate lower than 4.9×10-7 atm·cc/s have been obtained for Au46Sn54 solder bonded at 310 ℃.This wafer-level low cost bonding technique with high bonding strength can be applied to MEMS devices requiring low temperature packaging.     

A fixed frequency fast transient response DC-DC controller for VRM application Chen Mingyang(陈明阳), Zhao Menglian*(赵梦恋), Wu Xiaobo(吴晓波)

A 2V-10A fast transient response DC-DC buck controller based on fixed frequency hysteresis control is presented. A carefully designed output voltage filter detects the output capacitor current change which helps the controller to respond immediately after load changes. Adaptive hysteresis control guarantees the switching frequency to be the same as the reference frequency by using a CCII-composed circuit and current mirrors. The controller is designed and fabricated in a TSMC 0.35 μm process. Simulation and test results show that this con- troller achieves a 20 μs settling time in one single switching cycle when load current changes from 1 A to the full load condition at 10 A.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.