一种1.8伏带有foldback过流过热保护的低压线性稳压器设计

This paper introduces the design of a l.8 V low dropout voltage regulator （LDO） and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO s power supply rejection （PSR） is about -58dB and -54dB at 20Hz and 1kHz respectively,the response time is 4μs and the quiescent currentis 20μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.     

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS process.The proposed circuit generates a precise sub-bandgap voltage of 1 V.The temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room temperature.The line regulation is 0.27%/V.The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,respectively.The chip area is 0.2 mm~2.     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

An ll-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

Abstract： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.     

交流提升与有源反馈补偿的无片外电容CMOS低压差稳压器

A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

一种连续输出的小失调开关电容带隙基准源

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator（QVCO） is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz（17.5%）.Measured tuning gain of the QVCO(K_vco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm².     

A current mode feed-forward gain control system for a 0.8 V CMOS hearing aid

A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly improves the total harmonic distortion（THD）by digital gain control.To attain the digital gain control codes according to the extremely weak output signal from the microphone,a rectifier and a state controller implemented in current mode are proposed.A prototype chip has been designed based on a 0.13μm standard CMOS process.The measurement results show that the supply voltage can be as low as 0.6 V.And with the 0.8 V supply voltage,the THD is improved and below 0.06%（-64 dB）at the output level of 500 mV_p-p,yet the power consumption is limited to 40μW.In addition,the input referred noise is only 4μV_rmsand the maximum gain is maintained at 33 dB.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

用于流水线ADC的频率自适应可编程MDAC电路

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.