首页 | 本学科首页   官方微博 | 高级检索  
相似文献
 共查询到20条相似文献,搜索用时 640 毫秒
1.
Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter(ADC)implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to + 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit (FOM) of 0.63 pJ per conversion-step.  相似文献   

2.
A dynamic range extension scheme applied to a time delay integration (TDI) CMOS image sensor (CIS) is presented. Two types of pixels with higher and lower conversion gain are adopted in the pixel array, which are suitable for capturing images in low and high illumination respectively. By fusing the two kinds of pixels' output signals in the process of TDI accumulation, a high dynamic range image can be achieved. Compared with the traditional multiple integration technique, no photoelectrons generated during the exposure time are discarded by the reset operation, and thus a higher level of signal-to-noise ratio (SNR) can be retained. A prototype chip with an 8 × 8 pixel array is implemented in a 0.18 μm CIS process, and the pixel size is 15 × 15 μm2. Test results show that a 76 dB dynamic range can be achieved in 8-stage TDI mode, when the SNR boost can reach 7.26 dB at 90.8 lux.  相似文献   

3.
陈茂兴  徐晨  许坤  郑雷 《半导体学报》2013,34(12):124005-4
Conventional GaN-based flip-chip light-emitting diodes (CFC-LEDs) use Au bumps to contact the LED chip and Si submount, however the contact area is constrained by the number of Au bumps, limiting the heat dissipation performance. This paper presents a flat surface high power GaN-based flip-chip light emitting diode (SFC-LED), which can greatly improve the heat dissipation performance of the device. In order to understand the thermal performance of the SFC-LED thoroughly, a 3-D finite element model (FEM) is developed, and ANSYS is used to simulate the thermal performance. The temperature distributions of the SFC-LED and the CFC-LED are shown in this article, and the junction temperature simulation values of the SFC-LED and the CFC-LED are 112.80 ℃ and 122.97℃C, respectively. Simulation results prove that the junction temperature of the new structure is 10.17 ℃ lower than that of the conventional structure. Even if the CFC-LED has 24 Au bumps, the thermal resistance of the new structure is still far less than that of the conventional structure. The SFC-LED has a better thermal property.  相似文献   

4.
This paper presents a millimeter wave (mm-wave) oscillator that generates signal at 36.56 GHz. The ram-wave oscillator is realized in a UMC 0.18 μm CMOS process. The linear superposition (LS) technique breaks through the limit of cut-off frequency (JET), and realizes a much higher oscillation than Jr. Measurement results show that the LS oscillator produces a calibrated 37.17 dBm output power when biased at 1.8 V; the output power of fundamental signal is -10.85 dBm after calibration. The measured phase noise at 1 MHz frequency offset is -112.54 dBc/Hz at the frequency of 9.14 GHz. This circuit can be properly applied to mm-wave communication systems with advantages of low cost and high integration density.  相似文献   

5.
Community Question Answering (CQA) websites have greatly facilitated users' lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics: social relations and an ask-reply mechanism. As users' behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers' concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named "Quora", and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users' ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.  相似文献   

6.
This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IPldB) at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.  相似文献   

7.
A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.  相似文献   

8.
9.
A 1.65-μm three-section distributed Bragg reflector(DBR) laser for CH4 gas sensors is reported.The DBR laser has a wide tunable range covering the R3 and R4 methane absorption line manifolds.The wavelength tunability properties,temperature stability and laser linewidth are characterized and analyzed.Several advantages were demonstrated compared with traditional DFB lasers in harmonic detection.  相似文献   

10.
A low power high gain gain-controlled LNA + mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA + mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA + mixer, a previous low power LNA + mixer, and the proposed LNA + mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.  相似文献   

11.
一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器   总被引:1,自引:1,他引:0  
A high linearity 1.575 GHz SiGe:HBT low noise amplifier (LNA) for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of +7.8 dBm and an input third-order intercept point of +1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.  相似文献   

12.
A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.  相似文献   

13.
A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.  相似文献   

14.
This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.  相似文献   

15.
A novel algorithmic method, based on the different stress distribution on the surface of thin film in an SOI microstructure, is put forward to calculate the value of the silicon piezoresistance on the sensitive film. In the proposed method, we take the Ritz method as an initial theoretical model to calculate the rate of piezoresistance ΔR/R through an integral (the closed area Ω where the surface piezoresistance of the film lies as the integral area and the product of stress σ and piezoresistive coefficient π as the integral object) and compare the theoretical values with the experimental results. Compared with the traditional method, this novel calculation method is more accurate when applied to calculating the value of the silicon piezoresistance on the sensitive film of an SOI pieoresistive pressure sensor.  相似文献   

16.
A programmable high precision multiplying DAC (MDAC) is proposed. The MDAC incorporates a frequency-current converter (FCC) to adjust the power versus sampling rate and a programmable operational am- plifier (POTA) to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW (10 MHz) to 63 mW (100 MHz) while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.  相似文献   

17.
用于无采保流水线ADC的高速低功耗低失调动态比较器   总被引:1,自引:1,他引:0  
A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier (SHA)-less pipelined analog-to-digital converters (ADC). Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.  相似文献   

18.
多层铜布线CMP后表面残留CuO颗粒的去除研究   总被引:2,自引:1,他引:1  
This article introduces the removal technology of CuO particles on the post CMP wafer surface of multi-layered copper. According to the Cu film corrosion curve with different concentrations of HEO2 and the effect curve of time on the growth rate of CuO film, CuO film with the thickness of 220 nm grown on Cu a surface was successfully prepared without the interference of CuC12.2H20. Using the static corrosion experiment the type of chelating agent (FA/O II type chelating agent) and the concentration range (10-100 ppm) for CuO removal was determined, and the Cu removal rate was close to zero. The effect of surfactant on the cleaning solution properties was studied, and results indicated that the surfactant has the effect of reducing the surface tension and viscosity of the cleaning solution, and making the cleaning agent more stable. The influence of different concentrations of FA/O I type surfactant and the mixing of FA/O II type chelating agent and FA/O I type surfactant on the CuO removal effect and the film surface state was analyzed. The experimental results indicated that when the concentration of FA/O I type surfactant was 50 ppm, CuO particles were quickly removed, and the surface state was obviously improved. The best removal effect of CuO on the copper wiring film surface was achieved with the cleaning agent ratio of FA/O II type chelating agent 75 ppm and FA/O I type surfactant 50 ppm. Finally, the organic residue on the copper pattern film after cleaning with that cleaning agent was detected, and the results showed that the cleaning used agent did not generate organic residues on the film surface, and effectively removes the organic residue on the water.  相似文献   

19.
The clustering of trajectories over huge volumes of streaming data has been rec- ognized as critical for many modem applica- tions. In this work, we propose a continuous clustering of trajectories of moving objects over high speed data streams, which updates online trajectory clusters on basis of incremental line- segment clustering. The proposed clustering algorithm obtains trajectory clusters efficiently and stores all closed trajectory clusters in a bi- tree index with efficient search capability. Next, we present two query processing methods by utilising three proposed pruning strategies to fast handle two continuous spatio-temporal queries, threshold-based trajectory clustering queries and threshold-based trajectory outlier detections. Finally, the comprehensive experi- mental studies demonstrate that our algorithm achieves excellent effectiveness and high effi- ciency for continuous clustering on both syn- thetic and real streaming data, and the propo- sed query processing methods utilise average 90% less time than the naive query methods.  相似文献   

20.
冯松  高勇 《半导体学报》2014,35(7):074010-6
Based on a submicrometer-sized SiGe-SOI waveguide, the coupling loss mechanism is analyzed between the submicrometer-sized SiGe-SOI waveguide and the fiber. The main sources of coupling loss are analyzed, and the mismatch loss of the mode field is the mainly lost during connection between the submicrometer-sized waveguide and the fiber. In order to reduce the mismatch loss of the mode field, the structure ofa nanotaper SiGeSOI waveguide with a nanometer-sized tip is adopted. By reducing the waveguide dimensions to increase the mode field size, coupling loss could be reduced between the waveguide and the fiber. Different mode field dimensions ofnanotaper SiGe-SOI waveguides and fiber are quantitatively analyzed, and the quantitative relationship between nanotaper SiGe-SOI waveguide dimensions and mode field dimensions are obtained. Finally, nanotaper SiGe-SOI waveguides are made, and the test and analysis have been done. The final experimental results accord well with the theoretical analysis. When the waveguide width is 0.5 μm, the minimum coupling loss of the SiGe-SOI waveguide is 0.56 dB/facet, and also the correctness of the design method and theoretical analysis are verified.  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号